[HN Gopher] Aegis - open-source FPGA silicon
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Aegis - open-source FPGA silicon
Author : rosscomputerguy
Score : 123 points
Date : 2026-04-05 05:50 UTC (17 hours ago)
(HTM) web link (github.com)
(TXT) w3m dump (github.com)
| blowback wrote:
| Excellent. Put me down for a couple.
| morphle wrote:
| me too please
| Bluebirt wrote:
| Neat project - there are already a couple of good open FPGA
| projects. Have a look at Dirk Koch's and the FABolous teams work.
| They are doing exceptional work.
|
| But all open FPGA projects miss the IO required for a good
| design. They do not have any serdes hardware nor DDR IO cells.
| LarsKrimi wrote:
| This project seems to have a serdes block which seems to wrap
| whatever is in the PDK. Didn't look too far down but from a
| cursory glance it looked like it was built for an internal
| clock of 50 MHz (clock default to 20 ns) with an oversampling
| of 8: 400 MHz
|
| If those numbers are at all right it puts it in useful
| territory. Very much so for a first spin
|
| For a first spin it looks overall pretty useful. The only
| nitpick I have would be that `operation` on the DSP tile should
| be from fabric instead of config (hardcoded in bitstream)
| otherwise I don't see a convenient way of resetting the
| accumulator(?)
| rosscomputerguy wrote:
| Thanks for the suggestion on the DSP. Maybe I'll add new DSP
| tiles that are reconfigurable and keep the config based DSP
| tiles. I designed Aegis's Terra 1 to be a "good enough first
| gen" so that's why things are the way they are. I didn't want
| to over commit on the design for a first generation.
| rosscomputerguy wrote:
| Yeah, I did see there's been attempts but none really satisfied
| what I wanted out of it. I do know of FABulous and it seems
| good but not quite what I wanted. You can see that aside from
| yosys and nextpnr, it is quite self contained and even provides
| a very easy way of defining new silicon with Nix.
|
| I know that IO is really the 2nd thing which sells FPGA's. I
| did design a basic serdes hardware that should just work for
| this first generation. I do want to do DDR IO cells in the
| future.
| morphle wrote:
| You can come work with us/for us and scale your SerDes design
| for us. That gets you actual wafer mask sets taped-out, a
| million chips and a WSI, not just test chips. A succesful
| SerDes will get you a job (at least in Europe).
|
| How fast will the SerDes run, 50 Mhz? It is not clear to me
| from the serdes_tile.dart source code. Can you share the
| verilog files?
| dizhn wrote:
| There's also an open source Authenticator software with the same
| name.
| mosaibah wrote:
| The gap this closes is real. IceStorm and Apicula gave you open
| tooling but you were still loading bitstreams onto someone else's
| closed fabric. Yosys/nextpnr same story. Aegis is the first time
| the fabric itself is auditable, which matters a lot for anyone
| building hardware that needs a complete trust chain from RTL down
| to GDS. The wafer.space + open PDK path makes it actually
| tapeout-able, not just a simulation exercise. Curious how the
| LUT4 fabric competes on density against GF180 commercial
| offerings, that's usually where open implementations get humbling
| logicchains wrote:
| How far away are we from being able to run a hobby Linux on
| something like that, a completely hardware-backdoor-free
| system?
| morphle wrote:
| You can already do that on several Risc-V chips with mmu.
| rosscomputerguy wrote:
| You can already port over a RISC-V SoC to Aegis. I have not
| tested that yet but it is something I really want to do.
| fecal_henge wrote:
| How do you verify that the fab produces the design
| authentically? They could create a security vulnerability only
| they know how to exploit.
| lnsru wrote:
| That's a nice theory. Fab is one thing, but there are
| afterwards packaging and testing facilities where silicon can
| be swapped. I worked for a short time for a military
| contractor. They don't X-ray every single chip. They just use
| it assuming the ordered chip is the one which was delivered
| by the markings on the package.
| jononor wrote:
| X-ray would be the traditional approach, though quite
| expensive. IRIS by bunnie is another approach that aims to
| bring cost way down. Ref
| https://www.bunniestudios.com/blog/2024/iris-infra-red-in-
| si...
| bgnn wrote:
| Because you can just look into it and see if it's what you
| sent fof production, and if not and the word gets out you are
| done as a fab. Fab business is about trust. You also should
| trust that your design isn't leaked to the competition.
|
| It's very common to xray the dies, especially for debugging.
| Also common is to etch it layer by layer, take photos and
| rebuild the circuit schematic, mainly for reverse engineering
| but I've seen companies doing it to their own dies too.
|
| Things get more blurry at the board level, the combinations
| of suppliers and service providers are endless.
| fecal_henge wrote:
| Is it possible to resolve features on advanced nodes with
| xray machines? Or the etch and photograph method?
| smj-edison wrote:
| As someone who has only dabbled with FPGAs before, this is
| incredible to see all the steps end-to-end for silicon
| development! I feel like the articles I've read always leave out
| details in one part or another, so it's interesting to see all
| the nix dependencies and build steps.
| morphle wrote:
| We make an asynchronous sea of gates runtime reconfigurable gate
| array chip very different from FPGA's but with the same use cases
| https://github.com/fiberhood/MorphleLogic/blob/main/README_M...
|
| The problem is you can make test chips like Aegis for around $10
| (depending on the yield, on how many of the first 1000 chips
| actually work) but they are just that, test chips.
|
| In the case of Morphle Logic we make wafer scale integrations
| (WSI) with 10 billion transistors at 180nm for $750. That yields
| around 300 million 'gates', the largest commercial FPGA's barely
| get to 3 million. So our Morphle Logic WSI is the largest and
| fastest (up to 12 Ghz) FPGA you could get if we can find a few
| hundred buyers who want to pay up front (crowdfunding). Please
| email me if you are interested in such a enormous fast FPGA.
|
| I'll buy an Aegis FPGFA test chip just to find out how hard it is
| to test a test chip.
|
| Good luck RossComputerGuy, I hope you get working chips back. The
| same fab and supplier lost our first taped-out chips in the
| mail... and then they went bankrupt.
| bgnn wrote:
| 12 GHz on 180nm? Sorry, that's not possible. What's the actual
| clock speed?
| morphle wrote:
| Morphle Logic is asynchronous logic so there is no clock.
|
| At 110nm I measured when a transistor was switching the
| second transistor on its output. I can prove it, can you
| disprove it?
|
| A consistent 12Ghz signal cascade was (repeatedly) tested and
| confirmed on a 28nm asynchronous chip [1].
|
| Why would it be impossible? [2].
|
| We measure 800 Ghz and teraherz clocks on niobium
| superconducting Josephson Junctions [3,4,5].
|
| [1] https://byrdsight.com/asynchronous-technology-has-its-
| time-f... ( See also on the slides in the video talk)
|
| [2] "If an elderly but distinguished scientist says that
| something is possible, he is almost certainly right; but if
| he says that it is impossible, he is very probably wrong." -
| Arthur C. Clarke
|
| [3] Ivan Sutherland Keynote Single Flux Quantum SFQ Ditigal
| Electronics Digital circuits totally distinct from Quan
| https://www.youtube.com/watch?v=KMVV3ErGSVY
|
| [4] https://www.researchgate.net/profile/Jerome-
| Pety/publication...
|
| [5] https://scholar.google.com/scholar?hl=en&as_sdt=0,5&qsp=3
| &q=...
| jononor wrote:
| Nice specs! Looking forward to seeing how this and the other
| projects on Waferspace goes. Being able to produce 1k chips at a
| reasonable price will hopefully do wonders for open hardware /
| open silicon.
| rosscomputerguy wrote:
| Yep, Aegis's Terra 1 is designed to be "good enough" for the
| first generation. I do plan on expanding the Terra family of
| FPGA's if there's enough interest. I do want to work my way up
| to 100k LUT's.
| jononor wrote:
| What are your thoughts on including a RISC-V hardcore along
| with the gates? Because for almost all projects I can imagine
| using FPGA for, I would want a microcontroller also. This
| might however be slightly colored by me being a
| software/firmware first type of electronics engineer.
| Thinking especially for the smaller gate counts, like under
| 10k - because there a soft CPU takes up very precious
| resources.
| rosscomputerguy wrote:
| I've definitely had a thought about doing a hard core
| RISC-V SoC on a dev board.
| morphle wrote:
| 1k chips for $4000 or $7000 at 180nm is (a lot) more expensive
| than 180nm at MOSIS or Europractice, I wound not call it
| reasonable, especially because the EDA software tools and PDK
| used are inferior.
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