[HN Gopher] M8SBC-486 (Homebrew 486 computer)
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       M8SBC-486 (Homebrew 486 computer)
        
       Author : rasz
       Score  : 64 points
       Date   : 2026-01-11 18:58 UTC (6 days ago)
        
 (HTM) web link (maniek86.xyz)
 (TXT) w3m dump (maniek86.xyz)
        
       | fecal_henge wrote:
       | Is that hard soldered RAM? Very modern!
       | 
       | You mentioned something about custom holes. What does that mean?
        
         | blacklion wrote:
         | I think, it means that it cannot be mounted in any standard
         | case, like AT (I know, there is no official AT standard
         | formally), ATX, uATX or ITX.
        
       | reactordev wrote:
       | HN hug?
        
         | webdevver wrote:
         | https://web.archive.org/web/20260117185107/https://maniek86....
        
         | globalnode wrote:
         | origin server fell over
        
       | jandrese wrote:
       | 4MB of SRAM would have cost an absolute fortune back in the day.
       | One of the more overlooked reasons behind the explosion of
       | personal computing power back in the 80s and 90s was the
       | invention and proliferation of DRAM which made it finally
       | affordable for people to have enough memory on the system to use
       | it for more than toy scale projects.
        
         | retrac wrote:
         | 4 MB of SRAM in the '80s would have been the main RAM of a
         | supercomputer.
         | 
         | We still use SRAM today. It's what level-1 cache and registers
         | are implemented with - actual flip-flops, can be toggled with
         | one cycle delay. Supercomputers used to make their _entire_
         | main memory out of SRAM, effectively the whole thing was L1
         | cache.
         | 
         | The 486 has an on-chip cache - 8 or 16 KB of SRAM. Very large
         | for the time.
         | 
         | Off-chip access to the DRAM involves wait states. The read or
         | write is stalled until the DRAM enters the appropriate state.
         | The 486 would also do block reads of 16 bytes at a time to fill
         | an entire cache line. This is around the time main memory and
         | the CPU became increasingly decoupled.
         | 
         | Avoiding all the complexity of managing DRAM is why hobbyists
         | use SRAM these days. Basically: to avoid cost. Ironic!
        
           | sidewndr46 wrote:
           | And large amounts of L1 cache do in fact cost a fortune
           | today!
        
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       (page generated 2026-01-17 23:00 UTC)