[HN Gopher] Loongarch Improvements with Box64
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       Loongarch Improvements with Box64
        
       Author : aaronday
       Score  : 52 points
       Date   : 2026-01-06 16:52 UTC (6 hours ago)
        
 (HTM) web link (box86.org)
 (TXT) w3m dump (box86.org)
        
       | thesnide wrote:
       | I'm wondering if we'll see some riscv extensions specifically
       | designed to improve x86/amd64 emulation, such as what the M1 and
       | other did.
        
         | Findecanor wrote:
         | Some upcoming chips are supposed to support switching
         | individual processes to x86's "TSO" memory model. That might be
         | the most significant extension that Apple has for x86
         | emulation: it allows eliding all memory fence instructions used
         | to adapt to the weaker memory model.
         | 
         | LoongArch could have instructions that emulate specific x86
         | behaviour and flags, but there is practically no documentation
         | available.
        
           | mort96 wrote:
           | Is it just "some upcoming chips" inventing their own
           | extensions? Or is this a standardized ARM extension?
           | 
           | Basically, will writing against these upcoming chips mean
           | writing one implementation for Qualcomm, one implementation
           | for Rockchip, one implementation for Samsung, etc? Or will it
           | just require one implementation for the standard ARM "switch
           | to total store ordering memory model" extension
        
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       (page generated 2026-01-06 23:05 UTC)