[HN Gopher] Nvidia GB10's Memory Subsystem, from the CPU Side
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       Nvidia GB10's Memory Subsystem, from the CPU Side
        
       Author : ingve
       Score  : 54 points
       Date   : 2025-12-31 12:43 UTC (10 hours ago)
        
 (HTM) web link (chipsandcheese.com)
 (TXT) w3m dump (chipsandcheese.com)
        
       | Neywiny wrote:
       | I don't understand on one of the later graphs the core to core
       | latency for strix halo goes out to 32 cores but he says only has
       | 16 cores?
        
         | wtallis wrote:
         | AMD's cores have SMT, allowing them to run two threads at a
         | time and appear to the OS and its scheduler as two logical
         | cores despite being implemented as a single physical core.
        
           | Neywiny wrote:
           | What pattern in the data shows that's what's being measured?
           | I would expect to see basically 0 latency between adjacent
           | "cores" then since L1 is shared per thread?
        
             | monocasa wrote:
             | Co resident threads might not get any speed up here since
             | coherency instructions are functionally operations on the
             | L2 cache.
        
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       (page generated 2025-12-31 23:00 UTC)