[HN Gopher] ETH-Zurich: Digital Design and Computer Architecture...
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       ETH-Zurich: Digital Design and Computer Architecture; 227-0003-10L,
       Spring, 2025
        
       Author : __rito__
       Score  : 106 points
       Date   : 2025-11-30 17:45 UTC (5 hours ago)
        
 (HTM) web link (safari.ethz.ch)
 (TXT) w3m dump (safari.ethz.ch)
        
       | nfreising wrote:
       | Onur Mutlu also posts his (great) lectures to YouTube:
       | https://www.youtube.com/@OnurMutluLectures
        
         | __rito__ wrote:
         | The link for this course's playlist is posted on the page.
        
       | panick21_ wrote:
       | Crazy how successful the ETH open source designs were. The pop up
       | in lots of places.
        
         | ur-whale wrote:
         | https://www.topuniversities.com/world-university-rankings
         | 
         | ETH is at 7
         | 
         | Not too shabby for such a tiny country.
        
           | slow_typist wrote:
           | Not too shabby, while ,,citations per faculty" is the
           | indicator that destroys science and isn't a very strong
           | predictor for teaching quality.
        
       | chompychop wrote:
       | Does anyone know how this course compares to the NAND2Tetris
       | course?
        
         | markus_zhang wrote:
         | You can check out Onur Mutlu's videos on YouTube. I'd say it is
         | much more demanding than NAND2Tetris.
        
       | jansommer wrote:
       | This is also the university that develops RumbleDB[0]. It uses
       | JSONiq as its query language which is such a pleasure to work
       | with. It's useful for dealing with data lakes, though I've only
       | experimented with it because of JSONiq.
       | 
       | [0] https://github.com/RumbleDB/rumble
        
       | throwaway31131 wrote:
       | Details on the ETH Zurich open source ASICs can be found here:
       | 
       | https://github.com/open-source-eda-birds-of-a-feather/open-s...
       | 
       | Presented at DAC 2025
        
         | amelius wrote:
         | Is it even possible to design serious ASICs without expensive
         | tooling?
        
           | somethingsome wrote:
           | From the slides, they are reducing the gap, it's not there
           | yet.
           | 
           | But I was actually pleasantly surprised by how close they
           | are.
        
           | throwaway31131 wrote:
           | For some definitions of serious, sure. The main critical
           | piece that's missing is all the testing infrastructure.
           | Buying 100 or so ASICs for university use is one thing.
           | Buying 100K, or more, is another.
           | 
           | Not the gdb support via jtag that software engineers need,
           | they have that. But the various manufacturing test suites,
           | which do modify gate netlists, and automated circuit
           | characterization techniques that electrical engineers and the
           | manufacturing engineers use.
        
       | hannesfur wrote:
       | This course is actually mandatory in the first year of the CS
       | undergraduate program here at ETH. I remember it very fondly for
       | its great (and passionate) lecture and the hands on experience
       | building a MIPS cpu in the exercise sessions. Probably the best
       | lecture in my undergraduate.
        
       | outside1234 wrote:
       | Broadening the perspective here. Has anyone curated a complete
       | computer science / computer engineering curriculum here with
       | classes that are essentially "best of breed" on YouTube?
        
       | le-mark wrote:
       | Let's all take a moment to remember Nikolas Wirth and Project
       | Oberon and its fpga processor. I learned so much from reading his
       | books. They are very accessible and I recommend them to anyone!
        
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       (page generated 2025-11-30 23:00 UTC)