[HN Gopher] Driving TFEL with RP2040: Offloading the CPU step by...
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       Driving TFEL with RP2040: Offloading the CPU step by step (2021)
        
       Author : starkparker
       Score  : 21 points
       Date   : 2025-11-09 00:03 UTC (6 days ago)
        
 (HTM) web link (www.zephray.me)
 (TXT) w3m dump (www.zephray.me)
        
       | deivid wrote:
       | These screens look amazing, but $1500-2500 is a bit much. Any
       | other screens with this monichrome CRT style?
        
       | marcosscriven wrote:
       | Always impressed with the PIO capabilities.
       | 
       | Reminds me of the old BeagleBone Black that had two small
       | separate cores that worked in a similar way. Someone used it to
       | create a 3D printer control system.
       | 
       | Are there any other chips out there like this?
        
         | bri3d wrote:
         | Application / realtime split cores are very common, STM32MP*
         | was designed around the application processor / realtime
         | processor split, I don't remember if that's what was on that
         | Beaglebone. Any "big" application processor these days will
         | have a variety of smaller generic cores (Cortex-M style) around
         | it, some which usually handle programmable I/O.
         | 
         | A lot of microcontrollers also have pretty sophisticated
         | interrupt controllers and timing analyzers which can be used to
         | accomplish similar tasks, although they're usually "programmed"
         | by chaining register effects so it's nowhere near as elegant as
         | PIO.
         | 
         | Specialized IO coprocessors which are programmed using "code"
         | like PIO is are a little less common, Infineon Peripheral
         | Control Processor springs to mind.
        
           | marcosscriven wrote:
           | I just refreshed my memory - they were called Programmable
           | Realtime Units on this chip: https://uk.rs-
           | online.com/web/p/microprocessors/1219716
           | 
           | Can the "little" cores in big.little arches be run entirely
           | independently then? That's pretty cool if so.
        
             | bri3d wrote:
             | > Can the "little" cores in big.little arches be run
             | entirely independently then?
             | 
             | Well, that too :) What I'm referring to is more like
             | Qualcomm "safety island" on Dragonwing, Xilinx RPU, or
             | Allwinner AR100 (I think this is used in 3D printer
             | projects using A64, actually), though - where most modern
             | large "embedded" Linux SoCs have some real time island to
             | talk to the outside world. Cell phone SoCs and stuff like
             | Apple M also have realtime cores hiding in them running
             | blobs, although they're usually connected to more specific
             | RF or A/V blocks rather than generic IO.
        
           | 15155 wrote:
           | > Specialized IO coprocessors which are programmed using
           | "code" like PIO
           | 
           | Which is exactly what GP was talking about: the TI PRU cores
           | are this.
        
             | bri3d wrote:
             | Yeah, I didn't realize those were in a Beaglebone ever, I
             | thought it was STM32MPx. So that's like PIO or PCP more
             | directly.
        
       | mmastrac wrote:
       | Ooh. I've been putting together a VT420 emulator and I am trying
       | to figure out the best way to build one from scratch. I will
       | probably end up building an RP2040 version of the video
       | controller.
       | 
       | These look great, but I wonder if there's an 800x420ish version
       | out there.
        
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       (page generated 2025-11-15 23:02 UTC)