[HN Gopher] AMD's EPYC 9355P: Inside a 32 Core Zen 5 Server Chip
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       AMD's EPYC 9355P: Inside a 32 Core Zen 5 Server Chip
        
       Author : rbanffy
       Score  : 51 points
       Date   : 2025-10-03 20:01 UTC (2 hours ago)
        
 (HTM) web link (chipsandcheese.com)
 (TXT) w3m dump (chipsandcheese.com)
        
       | flumpcakes wrote:
       | The first picture has a typo on it's left hand side.
       | 
       | It says 16 cores per die with up 16 zen 5 dies per chip. For zen
       | 5 it's 8 cores per die, 16 dies per chip giving a total of 128
       | cores.
       | 
       | For zen 5c it's 16 cores per die, 12 dies per chip giving a total
       | of 192 cores.
       | 
       | Weirdly it's correct on the right side of the image.
        
       | haunter wrote:
       | >768 GB of DDR5-5200. The 12 memory controllers on the IO die
       | provide a 768-bit memory bus, so the setup provides just under
       | 500 GB/s of theoretical bandwidth
       | 
       | I know it's a server but I'd be so ready to use all of that as
       | RAM disk. Crazy amount at a crazy high speed. Even 1% would be
       | enough just to play around with something.
        
       | ashvardanian wrote:
       | Those are extremely uniform latencies. Seems like on these CPUs
       | most benefits from NUMA-aware thread-pools will be coming from
       | reduced contention - mostly synchronizing small subsets of cores,
       | rather than the actual memory affinity.
        
         | PunchyHamster wrote:
         | Well, all of the memory is at IO die. I remember AMD docs
         | outright recommend to make processor hide NUMA nodes from the
         | workload as trying to optimize for it might not even do
         | anything for a lot of workloads
        
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       (page generated 2025-10-03 23:00 UTC)