[HN Gopher] ZeroRISC Gets $10M Funding, Says Open-Source Silicon...
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ZeroRISC Gets $10M Funding, Says Open-Source Silicon Security
Inevitable
Author : wslh
Score : 22 points
Date : 2025-06-29 20:48 UTC (2 hours ago)
(HTM) web link (www.eetimes.com)
(TXT) w3m dump (www.eetimes.com)
| tonetegeatinst wrote:
| When we discuss the security of silicon, and are calling it open
| silicon, is this because the design specs and libraries are all
| open source, or is it due to being able to do research on chip
| attacks without fear of being sued?
| transpute wrote:
| The hardware IP is Apache-licensed,
| https://github.com/lowRISC/opentitan. Ideally, it will be
| possible to buy commercial hardware that incorporates an open
| silicon RoT, perform a reproducible build of open firmware for
| the device RoT, then sign and install firmware with the device
| owner's key.
|
| From OP:
|
| _> Moving away from unverifiable 'black boxes' and towards
| fully transparent and verifiable foundations unlocks a new
| paradigm, putting device owners back in control of their
| remotely connected devices without requiring physical diligence
| by hardware manufacturers.. assurance-first approach ensures
| that security starts below the operating system, offering
| protection against the most sophisticated hardware and firmware
| attacks and more common software vulnerabilities._
| transpute wrote:
| Hopefully 2025 will be the year of open-source silicon + open
| firmware RoT!
| https://opensource.googleblog.com/2025/02/fabrication-begins...
|
| For client devices, https://lowrisc.org/news/lowrisc-a-decade-of-
| bringing-open-s... _> OpenTitan's "Earl Grey", will be the plan
| of record hardware RoT for [2025] Chromebooks.. Caliptra, another
| open source Root of Trust project with wide industry adoption,
| has incorporated a considerable amount of OpenTitan's IP into its
| design.. OpenTitan's CPU core, the Ibex RISC-V microcontroller,
| is an important project in its own right.. Microsoft based its
| CHERIoT-Ibex design on lowRISC's commercial-grade Ibex CPU core,
| extending it with the proven CHERI hardware security extensions._
|
| For servers, https://github.com/chipsalliance/Caliptra &
| https://146a55aca6f00848c565-a7635525d40ac1c70300198708936b4...
|
| _> Caliptra consists of IP and firmware for an integrated Root
| of Trust block.. targets datacenter-class SoCs like CPUs, GPUs,
| DPUs, TPUs.. implementing a Root of Trust for Measurement (RTM)
| block inside an SoC. A Caliptra integration provides the SoC with
| Identity, Measured Boot and Attestation capabilities._
|
| https://opentitan.org/book/doc/use_cases/index.html &
| https://github.com/Microsoft/ms-tpm-20-ref
|
| _> OpenTitan can be used to implement the full Trusted Platform
| Module (TPM) 2.0 specification to meet client and server platform
| use cases._
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(page generated 2025-06-29 23:00 UTC)