[HN Gopher] OpenSERDES - Open Hardware Serializer/Deserializer (...
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       OpenSERDES - Open Hardware Serializer/Deserializer (SerDes) in
       Verilog (2020)
        
       Author : peter_d_sherman
       Score  : 76 points
       Date   : 2025-06-18 03:41 UTC (19 hours ago)
        
 (HTM) web link (github.com)
 (TXT) w3m dump (github.com)
        
       | peter_d_sherman wrote:
       | Related (book):
       | 
       | "High-Speed Serial I/O Made Simple: A Designers' Guide, with FPGA
       | Applications" (2005):
       | 
       | https://www.xilinx.com/publications/archives/books/serialio....
        
         | checker659 wrote:
         | Thank you. Any other recommendations?
        
         | addaon wrote:
         | Note that this book is about using the hard SerDes IPs included
         | in Xilinx FPGAs, while the top source link is about designing
         | your own SerDes.
        
           | nsteel wrote:
           | Looks to be plenty of general high-level serdes ideas and
           | theory in that xilinx pdf. But it is 20 years old (in
           | addition to FPGA being some years behind state of the art).
        
       | jauntywundrkind wrote:
       | Really awesome to see. Any kind of PHY type thing is awesome to
       | see.
       | 
       | It's an under-told tale that open CPU's are "easy" to make, but
       | if you actually want to actually run that chip it's everything
       | else that makes it inordinately hard.
       | 
       | Probably like 99.9% of devices with USB hosts all use the same
       | 4-5 different design families of host controllers. A huge number
       | of sound chips are Cadence/Tensilica's HiFi 4/5 chip. Dram
       | controllers, PCIe blocks... There's so many modular blocks used
       | in making chips, where a pre-qualified design that already has
       | been validated on a variety of fabs is just how everyone does it.
       | 
       | This is a 5 year old, barely updated project. There's no clear
       | data on what was achieved that I can see here. But just getting a
       | start doing chip design that interfaces with the world beyond the
       | chip is a huge huge step forward. Building, characterizing what
       | we get, tweaking & trying over again is what it's gonna take to
       | make open source chips emerge & be able to stand on their own.
        
         | Aromasin wrote:
         | I work in the FPGA industry, and it's a running joke that the
         | best device manufacturer at any one time if the one with the
         | best SERDES and PHY team.
         | 
         | You can have the best fabric in the world with all of the best
         | IP, but if you can't get information on the device and off
         | again to do anything useful, then what's the point (looking at
         | you Intel F-Tile).
        
           | gizajob wrote:
           | See: Blackmagic Design for phenomenal investment in SERDES
           | brains and how it shows in their world-beating products.
        
       | gchadwick wrote:
       | I wonder if they ever taped this out and did some device
       | characterization?
       | 
       | The devil really is in the details with things like this. 1 in 10
       | million events which may be hard to trigger in a detailed
       | analogue simulation can occur many times per second when you run
       | it in silicon and make it effectively useless.
       | 
       | Still very cool to have enough open source tooling and a PDK so
       | this can even be attempted as a piece of open source design work!
        
         | cushychicken wrote:
         | This was my first thought too.
         | 
         | RTL is all well and good. How does it perform in _silicon?_
        
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       (page generated 2025-06-18 23:01 UTC)