[HN Gopher] Post-Silicon Validation of Static Lockstep Mode
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       Post-Silicon Validation of Static Lockstep Mode
        
       Author : luu
       Score  : 29 points
       Date   : 2025-04-15 17:21 UTC (5 hours ago)
        
 (HTM) web link (www.intel.com)
 (TXT) w3m dump (www.intel.com)
        
       | trebligdivad wrote:
       | Is this limited to lockstep between softcores on a die - so good
       | for low level error failures like soft error, but no good if the
       | package dies? (Still very neatly done)
        
       | electricshampo1 wrote:
       | Nice to see SDC concerns being taken more seriously by hardware
       | folks. Once software gets to sufficient quality (which we have
       | achieved in many cases), these kinds of rando hw issues are the
       | only remaining causes of "impossible" bugs that waste endless
       | engineering time to debug.
       | 
       | I wonder how much of this relies on or is made easier by the
       | clustered core architecture of E-Core Xeons. In comparison each
       | physical core of P-Core Xeons is its own island basically.
        
       | bombela wrote:
       | I wonder what is the ratio of software vs those type of hardware
       | bugs in the wild. Maybe the product of this paper will help
       | produce this metric.
        
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       (page generated 2025-04-15 23:00 UTC)