[HN Gopher] MESI Cache Coherency Protocol Visualization
       ___________________________________________________________________
        
       MESI Cache Coherency Protocol Visualization
        
       Author : wizerno
       Score  : 18 points
       Date   : 2025-02-10 00:35 UTC (3 days ago)
        
 (HTM) web link (www.scss.tcd.ie)
 (TXT) w3m dump (www.scss.tcd.ie)
        
       | ajross wrote:
       | Obviously cache snooping is going to be device-dependent, but the
       | way this shows things happening is that if you write an address
       | that exists in another CPU's cache, that the invalidation doesn't
       | happen until that CPU later tries to read the address. That
       | requires two snoop cycles be dedicated, which is a waste. The
       | secondary CPU is already listening to the snoop bus, it
       | can/should (and in practice does on basically all devices, AFAIK)
       | be able to recognize that write fly by and free up its cache line
       | preemptively.
        
       ___________________________________________________________________
       (page generated 2025-02-13 23:00 UTC)