[HN Gopher] PCBs, copper pours, ground planes, and you
___________________________________________________________________
PCBs, copper pours, ground planes, and you
Author : surprisetalk
Score : 214 points
Date : 2025-01-30 04:33 UTC (18 hours ago)
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| fargle wrote:
| @dang title is wrong ground _planes_ not plates
| dang wrote:
| Fixed. Thanks!
| mmcwilliams wrote:
| I don't see it mentioned here but I may be too much of an amateur
| but I use copper pours because it reduces the work my ferric
| chloride has to do when I'm making prototypes. Having a mask
| cover all unused areas on the board vs. letting the acid eat
| through it seems like a waste.
| nickff wrote:
| Your logic is definitely sound for a hobbyist or prototyped,
| but the copper dissolved off a board in a commercial setting is
| recycled.
|
| The article misses the real reason why pours were uncommon in
| the 80s, which is that people had to actually "tape out" the
| whole thing, and it was very annoying to do pours that way.
| murderfs wrote:
| Lots of manufacturers will add copper pours to your board
| unless you explicitly tell them not to, for electroplating
| reasons. Here's a link to a JLCPCB post about it:
| https://jlcpcb.com/blog/the-importance-of-copper-pour-in-
| emp...
| mordae wrote:
| JLC never added the pour for me. Not even for larger
| boards. Not sure this is up to date.
|
| In any case, if you have to add the top layer pour, make
| sure to:
|
| 1. Use high clearence so as not to introduce edge coupling
| that changes your carefully calculated trace impedance.
|
| 2. Stitch the pour to actual GND with vias. Thoroughly. Do
| not let it float.
|
| You do calculate trace impedance, right? :-)
|
| I am only half joking. Some components let you specify
| source impedance. RP2040 has GPIO drive strength in mA, but
| they roughly correspond to 12 mA / 33 Ohm, 8mA / 50 Ohm, 4
| mA / 70 Ohm and 2 mA / 100 Ohm. I usually use 100 for 2
| layer boards and 70 for 4 layer boards. This is effectively
| series termination.
| bogantech wrote:
| > JLC never added the pour for me. Not even for larger
| boards. Not sure this is up to date.
|
| It seems to depend on the design - how close you are to
| the design limits and how much copper is exposed on the
| outer layers.
|
| A message someone got from JLC for an open source project
| recently:
|
| > When the copper pour is less than 30% of board area, we
| suggest to keep at least 0.15mm trace spacing.
|
| > Or the dry film debris might have chance make short
| circuit, it will make quality control more difficult
| cillian64 wrote:
| That article says that they only add copper in the
| handling/bridging parts of the panel, not to the actual
| finished PCB.
| thenthenthen wrote:
| Same goes for milling a pcb!
| exmadscientist wrote:
| Grumble grumble. Professional here, and I _really_ do not like
| this article.
|
| There are a lot of things getting mixed up here: ground planes
| for EMC, ground planes for electrical performance, ground planes
| for DFM/etching, and ground planes as "fashion".
|
| First off, let's just say that meeting radiated EMC ("47 CFR Part
| 15" according to the article, equivalent to CISPR 22/32 in
| Europe) is a bloody good idea. Yes, the testing labs are "a bit
| of a racket". But does anyone else remember the days when turning
| on the vacuum cleaner would knock out the TV? That wasn't great.
| And we have a whole lot more electronics in the world today. A
| world without Part 15/CISPR is an ugly world indeed.
|
| Four-layer boards are cheap. Really cheap. They may be double the
| cost, but you're doubling pennies here. In fact, just checking in
| with one common low-volume supplier, they're not doubling: the
| price for 200mm x 100mm boards with good specs goes from $9.34
| each in quantity 10 to... $10.59. For prototypes, that's
| basically a rounding error. Perhaps even literally a rounding
| error. So don't complain about the cost of four-layer boards
| anymore, it isn't 2004.
|
| Internal ground fill layers are what people usually mean when
| talking about "ground planes". They have three key properties:
|
| 1. They are very easy to do and are very tolerant of mistakes.
| You don't have to calculate return current paths, you don't have
| to size and locate return current traces, you don't have to gum
| up your routing. You just dedicate the layer and it works, and it
| keeps working if you have to make changes later.
|
| 2. They help shield internal layers further down in the stack
| from radiating. This is usually minor, but for nasty digital
| stuff or high-power electronics, can be useful.
|
| 3. They develop inter-plane capacitance with nearby power layers,
| if inter-layer dielectrics are small. This is critical to
| maintaining power distribution network performance at high
| frequencies (>100s of MHz). This stuff is very, very important to
| make high-speed digital logic work well. Of course, it's only one
| link in the chain (GHz stuff gets handled on-package or even on-
| die; <100MHz is the job of on-board capacitors until you get into
| power supply dynamics in the kHz and below). This is the
| "increasing shunt capacitance" mentioned in the article. Yes, it
| can be bad news for analog stuff, but this is both very rare and
| the sort of problem where anyone who can do that kind of
| difficult analog design has the skill to punch a hole in the
| plane where it's needed.
|
| There is also a manufacturing issue where the manufacturers find
| it easiest to have approximately balanced amounts of copper on
| opposite layers of a board. Copper pours are one solution to
| this. Copper thieving pads are another. This is important but
| easy to manage, and vendors are good at it.
|
| So all of the above applies to internal layer copper fills. None
| of it is "fashion": there are good reasons to do it, the extra
| layers are cheap these days, and it's an easy and robust way to
| design things. Fills on _external_ layers are a different matter;
| they 're kind of stupid in a lot of cases. Unless you're doing a
| two-layer design, or a 4-layer that kind of ends up behaving like
| a 2-layer (this happens sometimes when stuff is very tight), the
| external fills are pretty worthless. I wrote more about this ages
| ago over here: https://www.eevblog.com/forum/eda/altium-article-
| on-never-us... This is the only real thing I'd agree with the
| article on.
|
| There's a lot of stuff going on here, and I don't think this
| article does a very good job keeping it straight. If you take one
| thing away from all of this, it should probably be that internal
| copper planes are pretty great, and what happens on the outside
| of the board isn't so important.
| antigeox wrote:
| I don't think the article's audience are professional EEs/PCB
| designers otherwise they'd know all of this stuff and then
| some. So anyone serious should probably seek out a better
| reference.
| exmadscientist wrote:
| That's a reasonable take, but in my opinion, is not what a
| non-expert reading of this article seems to be suggesting. So
| I wanted to state the alternative case.
| jimnotgym wrote:
| I have some experience that tells me that not all
| professional PCB designers know this stuff...
| femto wrote:
| A reason for more external copper pours might also be that the
| EDA tools have improved and can now handle the complex shapes.
| Back in the 80s/90s copper pours were a pain using Protel
| (later called Altium), as they were built using straight tracks
| rather than polygons. Eventually the program got actual
| polygons and life became easier.
| vantablacksheep wrote:
| Going by the inconsistent spacing and angles on that 1984
| PCB, I'd almost guarantee that it was routed using black tape
| on mylar film, not a CAD package to be seen. Trying to create
| large fills back then would require manual positioning of
| tape over all of the copper fill areas. Tools is a big part
| of the reason for the shift, it's easy now, and the results
| are generally much better.
| exmadscientist wrote:
| I think that one was actually done in an early Japanese
| computerized CAD package. There's a lot of weird crap in
| that layout, but it's the sort that the old-school computer
| layout programs made, not the sort that humans did. Take a
| look around U111 pin 30, or south of R112, or, heck, any of
| the text. Whereas there's no sloppy-but-OK vias or wobbly
| text or anything like that.
| willis936 wrote:
| I actually prefer using plane layers with tracks to split to
| the messiness of polygon pours. It signals design intent to
| users and fab houses and doesn't require a ton of rules and
| calculations. Polygon pours have their place in top/bottom
| power nets.
| bartlettD wrote:
| Piggybacking onto this comment, but another reason for
| external pours is thermal performance. A copper pour on the
| surface on the PCB allows heat to convect off the board more
| easily. The gains aren't massive, but they can help as part
| of a larger thermal management scheme.
|
| I've also heard, possibly apocryphally, that in the old days
| when we used harsher chemical etchants, removing all of the
| copper from unused sections of the PCB would increase the
| risk of thinning the traces beyond what was intended. So in
| those cases a copper pour would reduce the time the PCB would
| need to spend in the etchant bath.
| petsfed wrote:
| I've worked with several stepper motor driver ICs that
| feature a ground pad on the bottom of the IC and recommend
| an unmasked copper pour connected to the ground pad via
| thermal vias, on the opposite side of the board from the
| IC, sized at least as big as the IC itself. Like, the
| manufacturer's suggestion is literally to use the copper as
| a heat sink. If you wanted, you could then affix dedicated
| heat transfer features, like a traditional finned heatsink,
| or a heat pipe to a dedicated cooler.
| exmadscientist wrote:
| Thermal pads are wonderful. Most of the time for moderate
| thermal loads, an exposed pad soldered to an internal
| ground plane running through the whole board is enough,
| as the copper layer there spreads out the heat well
| enough to dissipate. It always amazes me that an outer-
| layer copper fill is not much better than an inner-layer
| one, so the larger coverage of the inner layer wins every
| time.
|
| A great app note on getting started with thermal design
| from TI: https://www.ti.com/lit/an/snva183b/snva183b.pdf
| aidenn0 wrote:
| So is the default for a 4-layer board something like
| components/ground/power/components?
| exmadscientist wrote:
| Yep. And then for 6 layers, depending on the actual needs of
| the design, it'll often be components/ground/signal or
| power/signal or power/ground/components. Some designs need a
| lot of signal routing space. Some need a lot of split power
| rails. And some are nice and easy and don't need either.
| mordae wrote:
| Yes and it sucks people copy this.
|
| The default should be X / GND / X GND to maintain tight
| coupling of both signals and power to the GND plane and
| stitch the GND planes together with vias close to any other
| via that changes layers to maintain return paths.
|
| Power should be routed normally, except it should use widest
| practical traces and get decoupled with C close to ICs that
| consume it.
|
| But in any case, you always need to think about the signal
| and return. Even for power. It's never truly DC.
|
| If you do the "classic" signals / GND / VDD / signals, you
| are routing over VDD plane and your ground is waaay farther.
| Means all accidental VDD noise (you can't pinpoint, because
| it takes frequency dependent paths across the VDD/GND C) gets
| coupled into your signals on the back side.
|
| So don't do that.
| exmadscientist wrote:
| I don't follow you.
|
| The standard configuration, with a "fat core", is pretty
| much the best you can do in 4 layers for a "modern" design.
| By "modern" I mean something with a dense component load,
| probably double-sided load, and random-ish routing (so,
| exactly the opposite of the old '80s TTL design shown in
| the article image we're discussing in sibling comment). All
| the "better" 4-layer stackups require outer layers to be
| doing a lot of heavy lifting, which they cannot do if they
| are filled with parts. When you assume they have to be
| filled with parts -- because if they aren't filled with
| parts then _I can make it smaller_ and people want that! --
| then you just cannot use that space as anything else. Henry
| Ott discusses a number of stackup options for four layers,
| and the standard one is the only option of his that
| survives with this restriction. If you don 't like that,
| tough, I guess you're paying for 6 or 8 layers. Which isn't
| too bad these days!
|
| You complain about power (VDD) plane noise. This might be
| important in ultra-low-noise design, I don't know, I try
| not to do that sort of work. In normal work it is not a
| factor. Your power and ground planes should be connected by
| a pretty thick network of capacitors, so they are
| transparent to each other. Your power plane is as good as a
| ground plane for AC, and AC is the only thing that's hard
| to deal with. So there is no issue routing the bottom layer
| on the other side of power, not ground. (Of course, that is
| no longer true if your power plane is split. Split power
| planes in a high-speed 4-layer design can be nasty, and are
| how I justify my worth to my employers!)
| mordae wrote:
| https://m.youtube.com/watch?v=60RxCiZuD9E
|
| Rick Hartley explains.
| exmadscientist wrote:
| I don't think you are arguing for the same thing as
| Hartley. I strongly approve of some things he says:
| "people believe that just pouring ground on top and
| bottom lowers EMI... well it doesn't!" (6:04) or "there
| is no four layer stackup that's wonderfu... no 'gosh,
| isn't that great?' four-layer stackup, they just don't
| exist, it's four layers, you know, you can only do so
| much with it" (7:29). No mention of VDD noise or
| discussion of how a good, well-decoupled power plane is
| basically as good as a ground plane for AC return
| currents.
|
| I believe you are trying to get a stackup that supports
| use of stripline for signals. That is a reasonable goal
| but it is only appropriate for very high speed digital
| designs. If you route stripline on a regular basis,
| you're either very experienced or clueless. No middle
| ground!
|
| Really, for heavy-duty work, you need six. And you can
| argue with me, and say that by great skill you can get
| things into four layers, and that is true. But six-layer
| boards are _cheap_ compared to what they used to be, so
| for anything not going into true high-volume
| manufacturing, just go for six or eight. In all other
| cases, the design cost hit will outweigh the parts cost
| savings.
| the__alchemist wrote:
| Nailed it. This was confusing to me too hearing about
| other stacks, as they stopped being effective once I used
| the top (And sometimes bottom) for components, which
| happens on every design I make. If not, I'd shrink the
| design! EM concerns aside, I want easy access to power
| and ground.
| lnsru wrote:
| Signal is a wide definition of possible traces. Signal can
| be status LED toggling every 3 seconds, it can be I2C in
| kHz range or SPI running 80 MHz or 100Mbps Ethernet. I
| don't mind routing slow signals over power plane. For the
| fast ones I would go through pcb and route over GND plane
| with equal vias amount for each trace. So classic
| signals/GND/(split)VDD/signals is absolutely fine for
| simple applications.
| michaelt wrote:
| There are different options.
|
| If you put the power planes on the inner layers and the
| signal on the outer layers, it's much easier to visually
| inspect the signal layers. And if you got something wrong on
| the prototype and you have to fix it manually, the traces are
| right there where you can get at them.
|
| On the other hand, if you're doing some performance-critical
| RF wizardry, you might put the ground planes on the outer
| layers and the signal on the inner layers, sandwiching your
| signal between two ground planes. So if you look at a wifi
| module or something like that, sometimes the outer layers
| will have very few traces.
| dragontamer wrote:
| The default today is likely signal/ground/ground/signal.
|
| Or really, the default today is a 6 layer board because 4 is
| still kinda bad.
|
| Today's engineers know that signal-top has a return path
| through ground-top. But if you ever were to via a wire from
| signal-top to signal-bottom, the return path gets lost (aka:
| return path is now through the board or worse, through the
| air and radiating off of your board).
|
| To prevent this erratic behavior, you must continue to think
| about the return path and tie a via from ground-top to
| ground-bottom as close as possible to the via between signal-
| top and signal-bottom.
|
| --------
|
| 6 layer can do signal/ground/signal -core-
| signal/ground/signal
|
| Where core is the FR4 material (keeping the middle signals
| far enough apart that they likely don't interfere with each
| other). This allows vias between layer#1 and #3 without
| needing a secondary return via. (But if you need layer#1 to
| layer#6 via, then the previous advice still applies where
| ground-top needs a secondary return via to ground-bottom).
| neltnerb wrote:
| For anyone else that also wants a much more in depth
| explanation, this hour long talk is a gem.
|
| https://resources.altium.com/p/2-the-extreme-importance-
| of-p...
|
| That AC signal energy is contained in the field between the
| trace and it's return is such a powerful model compared to
| taking the DC model of "going the lowest impedance path"
| and just assuming it applies at AC. Very, very, very good
| talk.
|
| This model also automatically makes clear why you'd want
| signal-GND-GND-signal instead of a power plane because that
| side's signals will have coupling into the power plane. It
| is mentioned explicitly in the video as well.
| ansible wrote:
| If you don't need components on the bottom side, it saves
| money to not do so. That means the board doesn't need to go
| through another pass on the SMT machine.
|
| Even if a board is double-sided, it is common to avoid
| putting major ICs on both sides, unless the space constraints
| are severe. Often, people will only put passive components on
| the bottom side.
| lightedman wrote:
| "There's a lot of stuff going on here, and I don't think this
| article does a very good job keeping it straight. If you take
| one thing away from all of this, it should probably be that
| internal copper planes are pretty great, and what happens on
| the outside of the board isn't so important."
|
| And then this article totally ignores solid metal PCBs, which
| are my realm of specialty and have their own inherent
| challenges when it comes to digital equipment.
| kazinator wrote:
| One reason for copper pours in a DIY hobby context is that copper
| pours vastly reduce how much copper has to be etched away. This
| requires less chemical like ferric chloride and less time.
|
| You are making a capacitor, though, when you do that.
| mort96 wrote:
| Surely the capacitor effect isn't that significant if you add
| in a bunch of stitching vias though, right?
| yujzgzc wrote:
| All I know is that it makes it very hard to solder anything to
| ground with my cheap underpowered soldering iron
| pjc50 wrote:
| Can be improved with proper thermal reliefs!
| buildsjets wrote:
| Can be improved by purchasing a decent soldering iron, which
| seems like a reasonable step to take if you need to solder
| something more than once or twice.
| mikeInAlaska wrote:
| I switched away from full solid copper floods due to this.
| (Even with nice soldering equipment.) I still use full size
| floods but they are more like basket-weave patterns, probably
| 50% copper. I rotate the pattern on my second inner plane.
| michaelt wrote:
| _> Other than increased miniaturization, the most striking change
| is the use of copper pours [...] Why did we start doing this?_
|
| We've been doing something a lot like this for as long as I can
| remember.
|
| Back in the 1990s if there were any big unused copper areas on
| your PCB you'd mask them to save on etching acid - a gallon of
| acid would have a lifetime measured in square inches of copper
| removed, and the less copper you removed, the longer your acid
| would last.
|
| Meanwhile, a lot of DIY etching processes were very basic. Sure,
| you _could_ get translucent acid and a transparent bath and heat
| it to a controlled temperature and run bubbles through it and so
| on. But if you were on a budget, some room temperature ferric
| chloride in an old ice cream container would get the job done.
| And getting the etch resist onto the board? You could draw it by
| hand with special pens, use transfers, there were special printer
| toner transfer papers, or you could DIY UV photoresist using
| printable projector transparencies and the sun as your UV source.
|
| This was not a super-scientific, tightly controlled process.
|
| If you had narrow traces and narrow gaps on one part of your PCB,
| and large areas of copper to remove on another? Well, if you left
| it in the acid long enough to remove that large area, could be
| the narrow traces get etched away too.
|
| So masking off any large areas meant all the copper getting
| etched was about the same width - thus compensating for the
| poorly controlled etching process.
|
| Of course, these days professional PCB manufacturing is orders of
| magnitude cheaper than it used to be. When you send your design
| to pcbway or jlcpcb they have much tighter control over the
| process, so you no longer have to worry about this stuff.
| aylons wrote:
| Well, you may not have to worry, but if you have large unpoured
| areas on a design with a professional PCB manufacturer (of the
| traditional, high-touch kind), they will ask if you want to
| pour some copper there. Reason being that it makes the process
| faster, more consistent and reduce possible side-etching on
| lanes. It may not a make a difference in most cases, but you
| may just save some time and effort by doing this.
| iancmceachern wrote:
| The reason is that the copper is already there, it gets
| etched away. So it actually costs more to not have copper
| than to have it.
| HansHamster wrote:
| > When you send your design to pcbway or jlcpcb they have much
| tighter control over the process, so you no longer have to
| worry about this stuff.
|
| Funny that you mention jlcpcb. The last time I submitted a
| board with tight differential pairs (but still within their
| listed specs) to them they basically told me to increase the
| amount of copper, so I assume they had some quality issues in
| the past:
|
| > we have new rule since Dec, 2022, if the copper areas are
| less than 30% of the board in each copper layer, the space
| between trace and trace should be at least 0.15mm to avoid
| short circuit.
|
| So I had to add a few copper pours and everything was fine :)
| neltnerb wrote:
| Arguably, the fact that they knew in advance exactly what you
| would need to do to avoid the issue means their process
| control is incredible!
| cushychicken wrote:
| This article is a bit superficial on EMC compliance, but they get
| one thing right, and that's this:
|
| _Adding a solid ground plane to your board is one of the single
| best choices you can make in your PCB design._
| roland35 wrote:
| There are a few other benefit to copper fills as well - it makes
| routing power much easier, it separates analog and digital
| regions of a PCB, and it helps with heat dissipation.
|
| I do agree that just because you have a fill, that doesn't mean
| it is necessarily doing much help. You need to be careful that it
| isn't too broken up.
| MisterTea wrote:
| This is blogging for the sake of blogging. "A closer look at a
| fashion trend in printed circuit board design" reads like its
| going to be a history lesson in PCB aesthetics that quickly veers
| off into the weeds with copper pours that the author confuses
| with ground planes. There's no fashion or history here. Just
| another mostly useless article to pad out their blogger merit
| badge.
|
| If you want to write a genuinely useful technical article then
| have someone in the relative field read it and give feedback.
| Otherwise you are wasting peoples time or worse, misleading them
| and causing harm.
| pcdoodle wrote:
| Without a ground pour, isn't each trace basically an antenna?
| mort96 wrote:
| Well not if there's a ground plane beneath, with 4 layers you
| can have signal traces on the outer layers and make the inner
| layers ground and every trace will have a good ground
| reference.
|
| With a 2 layer board though, one layer's "copper pour" is the
| other layer's "ground plane"... Yet the article seems to
| advocate that you shouldn't use copper pours for 2 layer boards
| either? That's weird.
| tverbeure wrote:
| One of my all time favorite videos (one of the few that I rewatch
| once per year) is "The Extreme Importance of PC Board Stack-Up
| with Rick Hartley". It's fantastic.
|
| https://resources.altium.com/p/the-extreme-importance-of-pc-...
| cushychicken wrote:
| Hartley is awesome. Plus one for that.
| mikeInAlaska wrote:
| Four layer boards are so cheap now, it's all I choose. I usually
| do two internal ground planes and route my power on one side
| unbroken. I haven't made an interrupted return path since
| watching Rick Hartley videos.
| the__alchemist wrote:
| Great article!
|
| > To keep things simple, some hobbyists opt for four-layer
| boards, with the two inner layers dedicated to GND and Vdd. This
| works, but means paying about twice as much.
|
| With the prices out of Shenzhen, there is IMO no reason to use a
| 2-layer board, outside of trivial cases (Like a CAN terminator
| etc). 4-layers are a bit more expensive, but make routing much
| easier. I don't want to spend the time solving the routing puzzle
| on a two-layer board, then worrying about inductance (the
| article's topic) on top of that.
|
| Baseline 2024 plan: Start with 4-layers as a generic baseline. Go
| to 6 (or higher?) if your design is sufficiently complex, and/or
| complex. (Or has high-frequency signals). More layers = more
| easier.
| varispeed wrote:
| There is no reason to use 4-layers either. With 6 being so
| cheap, you can save time on routing and head scratching.
| bigstrat2003 wrote:
| Ok I'm gonna ask a potentially stupid question as someone who
| knows little to nothing about electronics. The article (and every
| other source I looked at when trying to answer my question)
| points out the blank spots on the board as a copper pour. Where,
| exactly, is the copper? I just see green plastic. Is it on the
| back side and nobody is taking photos of it?
| lexicality wrote:
| stupid answer: copper goes green when it oxidises
|
| actual answer: PCBs are covered in a protective film to prevent
| damage to the extremely thin layer of copper on them from bumps
| jrockway wrote:
| A PCB is a layer cake of fiberglass and copper, with the green
| stuff just being paint on top to make manufacturing easier. The
| copper is glued to the fiberglass and etched according to your
| design files. (This turns a plate of copper into a bunch of
| very thin wires, basically.) If it's a multi-layer design, a
| bunch of these etched boards are glued together. Holes are then
| drilled for vias (which are rivet like things that electrically
| connect arbitrary layers according to your design file) and
| through holes (for through-hole components, or for screws to
| attach a board to an enclosure, etc). Finally, a solder mask
| (the green stuff) is applied over the parts of the copper that
| don't need to be exposed (for connecting components), covering
| the copper on the outside layers.
|
| The solder mask prevents solder from sticking to parts of the
| board that don't need solder on them.
|
| To add components, solder paste (little balls of metal embedded
| in a flux) is applied to the areas without solder mask (using a
| metal plate that is laser cut to have holes where solder is
| needed), and then an optical/robotic system called a pick and
| place machine places each component at the right spot. (Or you
| can do this with tweezers.) Finally, the board is heated to the
| melting point of the solder, and because of the solder mask,
| pulls all the components into the exactly right place (by
| minimizing surface tension, something liquids like to do).
| Through hole boards are a little different, they get "wave
| soldered" where the board floats on molten solder and attaches
| to the metal areas. The solder mask is even more helpful here.
| If you didn't have solder mask, you'd just get a thick layer of
| solder on top of every trace, and potentially bridges between
| adjacent traces, which is bad. (But people do apply solder to
| exposed traces to increase their current carrying capacity.)
|
| TLDR, the plastic on top is paint that makes manufacturing
| easier. If you make PCBs in your own shop with a laser or mini
| CNC, you won't have solder mask, and you can see how much more
| difficult soldering components is. It's not impossible. Just a
| little bit more work from your hand and brain is required, and
| that's expensive at scale. So, plasticy paint.
| bigstrat2003 wrote:
| Thank you for the explanation! I had no idea about any of
| this, I figured that circuit boards were just plastic with
| metal traces etched in somehow. I didn't know that so much
| went into them.
| exmadscientist wrote:
| Every time I order these things I am astounded at how
| _cheap_ they are for what you get.
|
| Sometimes volume really is magic!
| kevin_thibedeau wrote:
| The simple explanation is that glue logic and wide busses have
| mostly disappeared from contemporary electronics. Now you have a
| smattering of peripherals with point to point links leaving board
| space for fills that would have been pointless attempting with
| pervasive Manhattan routing on the outer layers.
|
| Solid fills also had a propensity to warp boards, requiring
| hatched patterns to relieve the imbalance. That constrained their
| use to boards with sufficient free space to maintain connectivity
| of the fill areas. PCB manufacturing has improved enough to
| minimize this concern.
| dtgriscom wrote:
| > In electronic circuits, the flow of electrons is confined to
| conductors, but the transfer of energy doesn't involve these
| particles bouncing off each other; instead, the process is
| mediated through electromagnetic fields. These fields originate
| from charge carriers, but extend freely into the surrounding
| space.
|
| That's a great couple of sentences; it really clearly explains
| what's going on.
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