[HN Gopher] Gate-level simulation of ASIC in browser
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Gate-level simulation of ASIC in browser
Author : picture
Score : 170 points
Date : 2025-01-08 06:38 UTC (16 hours ago)
(HTM) web link (znah.net)
(TXT) w3m dump (znah.net)
| mikewarot wrote:
| I'm amazed. The technical wizardry involved in stuffing this into
| such a small area of Silicon, then simulating it in a web
| browser, is awe inspiring.
|
| At the same time I'm filled with doubt I can get my BitGrid to
| the same state.
| Taniwha wrote:
| You can do it too, come on over to https://www.tinytapeout.com/
| hgo wrote:
| I _need_ to tinytapout! Don't know what, don't know how, but
| the sense of need is tickling! I feel like twelve again in
| front of a 286 without a case.
| femto wrote:
| Interesting:
| https://www.tinytapeout.com/competitions/demoscene-tt10/
|
| This seems to be the currently open tapeout.
|
| How low-level can you go with tinytapeout? One can imagine
| the insanity of doing a manual layout to push a demo to
| extremes.
| Taniwha wrote:
| You can work at the polygon level if you really want to,
| you can write gates and have it lay them out for you (or
| place them yourself), or work in a higher level language
| like verilog and have it compile them into gates for you
| (what most people do) - your choice
| Lerc wrote:
| How good are things like verilog at producing efficient
| layouts?
|
| Coming from the perspective of software. Hand coded asm
| can usually squeeze a lot more than a compiler into a
| small number of bytes, but that's mostly due to compilers
| targeting speed of execution instead of size.
| gorkish wrote:
| Verilog describes the logic. This is extremely
| simplified, but you can imagine that verilog and other
| HDLs are "compiled" into a big schematic of logic gates
| and a big list of signal timing constraints between them.
| From that schematic and constraint list, a solver then
| works to do place and route.
|
| Both of these intermediate stages between verilog and the
| final working hardware are where all of the secret sauce
| in semiconductor design actually lives. Both of these
| steps will be affected by the process target. Are you
| building for an FPGA or CPLD? Which one? If for an ASIC
| what is the process node? What logic elements are
| available in your node? Just like when you order a PCB,
| the process design rules generally come with prescribed
| information about the manufacturing constraints -- what
| works and what doesn't. And ultimately you cant rely on
| hand layout to throw down millions/billions of circuit
| elements anyway so you have to build solvers and all
| kinds of other mind bogglingly sophisticated automation
| to the party.
|
| The diminishing returns of manual optimization here
| should be evident; if you want to do that work, become a
| process design engineer.
|
| We do need more open information in this space! Tiny
| Tapeout is such a great project!
| Lerc wrote:
| That's all very analogous to software compilers, but
| doesn't really answer the question I had.
|
| Specifically for Tiny Tapeout, how much is there to be
| gained by going low level? I feel like using a subset of
| verilog features might get you most of the way there.
|
| Consider that there is a 512 byte BASIC interpreter in
| asm, that's well beyond what a compiler could manage. I
| would expect logic expressions in verilog to get closer
| to a hand crafted approach than that, but I might be
| wrong.
| rasz wrote:
| Can be huge depending how low level you are allowed to
| go. For example from recent
|
| 38C3 - The Design Decisions behind the first Open-
| Everything FABulous FPGA
| https://www.youtube.com/watch?v=3Lll9_-gYGg
|
| there was a mention of using open source SRAM library
| versus Siemens one. Open source macros build 1KB 12MHz
| ram while siemens is 3x capacity 100MHz
|
| https://youtu.be/3Lll9_-gYGg?feature=shared&t=1740
|
| Siemens delivers this by breaking foundry design rules :)
|
| https://youtu.be/3Lll9_-gYGg?feature=shared&t=1878
| sans_souse wrote:
| Those baseball caps are BALLIN
| StringyBob wrote:
| See also virtual 6502 and ARM1 e.g.
| http://www.visual6502.org/sim/varm/armgl.html
| Aissen wrote:
| You might also want floooh's remix which has a nicer UI, with
| the ability to see instructions evaluated, modify memory,
| assemble/disassemble code, view traces, etc.
|
| Visual 6502 remix: https://floooh.github.io/visual6502remix/
| Visual Z80 remix: https://floooh.github.io/visualz80remix/
| butlike wrote:
| This is going to sound quaint, but because of this simulation,
| this is the first time I realized they're _literal_ flags on
| the sides of the CPU, which is blowing my mind.
| epcoa wrote:
| You mean the pads? Those are the connection points for the
| wires that connect to the external package pins.
| znah wrote:
| Author here, and this is how running your design on real hardware
| feels
| https://x.com/zzznah/status/1876684831222067350?t=b8-zl-h6uV...
| Aardwolf wrote:
| This is amazing, I assume the sections lighting on/off are
| getting electrically activated, but what is this yellow orb
| slowly moving from left to right near the top?
| croemer wrote:
| My hunch is that that's the pixel that's currently addressed?
| mark_undoio wrote:
| Looks like it - if you turn the simulation speed slider way
| up you can see the image forming as it passes over.
| jasonjayr wrote:
| It's the position of the electron beam in a CRT monitor --
| from the VGA signal the hardware is emitting.
| butlike wrote:
| Tyrell Corporation
| ge96 wrote:
| It looks visually cool
| tmvphil wrote:
| Completely wild to me that you are backing out the netlist from
| the geometry gds.
| znah wrote:
| First I implemented it, and then learned that it is called
| Layout vs Schematic (LVS). For now automatic conversion is
| limited to stateless cells, but I'm planning to rewrite the
| circuit extractor to support all flipflops and latches.
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(page generated 2025-01-08 23:00 UTC)