[HN Gopher] Hynix launches 321-layer NAND
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Hynix launches 321-layer NAND
Author : WaitWaitWha
Score : 39 points
Date : 2024-11-24 19:30 UTC (3 hours ago)
(HTM) web link (www.electronicsweekly.com)
(TXT) w3m dump (www.electronicsweekly.com)
| kridsdale3 wrote:
| When I was in school studying NAND devices (2004-2010) we were
| quite apprehensive at the long term quantum stability of 4-layer
| devices.
|
| This (the past 20 years of improvement) is an incredible feat of
| engineering.
| duskwuff wrote:
| This is 321 _physical_ layers of silicon in an IC, not 321
| charge levels.
|
| QLC flash - with 16 charge levels, for four bits per cell - is
| pretty common nowadays, but that's as far as it goes so far.
| And stability is indeed a concern; modern flash devices rely
| _heavily_ on error correction.
| hinkley wrote:
| Where's the point where you figure out how to stack chiplets
| perpendicular to a backplane instead of doing lithography 300
| times on the same chip?
| duskwuff wrote:
| That's kind of what we're doing already, although the stacking
| is parallel, not perpendicular. A lot of the innovation is in
| how the dies are tied together, cf.
| https://www.anandtech.com/show/9520/toshiba-brings-throughsi...
| creer wrote:
| This is an interesting testament to manufacturing reliability -
| that they can go to so many layers and still achieve good
| yield.
| fodkodrasz wrote:
| > triple level cell-based 4D memory
|
| What does 4D memory mean?
| matja wrote:
| Nothing - just marketing. It's their 2nd gen Periphery Under
| Cell (PUC) device.
| wrs wrote:
| It's marketing speak. 3D flash (stacked chips) with the control
| circuits stacked underneath instead of to the side. So it's one
| louder.
|
| https://www.tomshardware.com/news/sk_hynix-debuts-4d_nand,37...
| K0HAX wrote:
| Bigger number = more betterer
| Animats wrote:
| Wow. What's the yield like? Are some bits bad and bypassed during
| testing?
| timschmidt wrote:
| > Are some bits bad and bypassed during testing?
|
| Always. All digital storage media depends on error correcting
| codes and sector-remapping these days.
| Neywiny wrote:
| I just want smaller SPI flash for embedded :( it's been over 10
| years since there's been improvement in that space
| duskwuff wrote:
| WLCSP-8 is pretty damn small already, at ~1.5mm square. Hard to
| get much smaller.
| Neywiny wrote:
| But they aren't high capacity. As far as I've seen, we've
| been stuck on the same XY size 512 Mb dies for over a decade.
| Even now, Infineon is claiming they have a series that'll go
| up to 4 Gb but is still at the standard 2 Gb maximum. NOR
| hasn't gotten any denser in forever.
| duskwuff wrote:
| What's the use case for a NOR flash that large? Even at 2
| Gbit, you're probably better off with something optimized
| for density like eMMC.
| tomcam wrote:
| Cookie permission dialog is the worst I have encountered in
| months
| randomjoe2 wrote:
| Thank god for ublock origin filters, i have all the optional
| filter lists, I never see those things. EVER.
| StringyBob wrote:
| What does 'layer' mean in this context? I'm only familiar with
| planar style logic process nodes which have maybe up to 20 layers
| (and way more lithography steps to manufacture those layers), but
| I am completely ignorant of how the term is used for a flash
| process node.
|
| How many layers are needed for each physical cell? Is it 1,2, or
| a lot more? Is this effectively 320 physical QLC cells stacked
| vertically and some planar style logic at the bottom of the
| stack.
|
| Also, where do multiple pieces of silicon factor into this - I
| assume we might be up to 16 silicon dies deep with through-
| silicon-vias, which would mean a cross section of a package could
| actually have 5000 layers - that sounds crazy!
| brennanpeterson wrote:
| Probably done with 3 separate litho/etch layers, where they
| etch and process in groups of 110 or so.
|
| Each of those layers can have a cell, so if you have a tlc
| device at a 100nm pitch, you have a density of 321*3/(1e-4)^2
| bits/mm, or about 1e11bits/mm2.
|
| Fun reference: atomic density is 1atom/.5nm, so 1/5e-7^2, or
| 4e12/mm2 ish.
|
| Not too far away.
| RicoElectrico wrote:
| What's interesting is that these devices don't need 321+ litho
| steps; the vertical layers are all defined with deposition.
| Lithography step count isn't layer dependent it seems.
|
| https://youtu.be/ANHzVOiUwGI
|
| https://thememoryguy.com/3d-nands-impact-on-the-equipment-ma...
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