[HN Gopher] DIMM vs. Udimm vs. Rdimm vs. Sodimm vs. Cudimm: What...
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DIMM vs. Udimm vs. Rdimm vs. Sodimm vs. Cudimm: What's the
Difference?
Author : trelane
Score : 47 points
Date : 2024-11-17 05:31 UTC (17 hours ago)
(HTM) web link (www.corsair.com)
(TXT) w3m dump (www.corsair.com)
| Culonavirus wrote:
| Yeah, but what about CAMM2? I need MORE ACRONYMS!! ;)
| kvemkon wrote:
| Related:
|
| The Difference Between a Standard DIMM and a Cudimm or Csodimm
| [Crucial/Micron] (16.11.2024)
|
| https://news.ycombinator.com/item?id=42102076
| ComputerGuru wrote:
| This isn't really a deep dive into the tech, it's just an SEO
| placeholder for a company that sells memory modules.
|
| That aside, people usually learn about RDIMM the hard way when
| they need to get ECC unbuffered RAM for something like
| HEDT/workstation or tower server Xeon/i3/Ryzen with ECC support
| but buy the cheaper RDIMM instead of the ECC UDIMM modules only
| to figure out they don't work!
| throwaway48476 wrote:
| HEDT has disappeared. It's just server platforms with RDIMM
| now.
| buildbot wrote:
| Not true, the W790 chipset is purely for HEDT/workstations,
| distinct from the sapphire rapids server line. AMD also has
| an entire separate HEDT socket, sTR5 for threadripper CPUs.
| HEDT is alive and well!
| wtallis wrote:
| HEDT as a consumer product segment distinct from the
| workstation segment is pretty close to dead. Intel hasn't
| introduced a new HEDT socket since 2017 and hasn't launched
| any new CPUs for that platform since 2019.
|
| AMD's Threadripper line has been inconsistent; the 5000
| series was all Threadripper PRO parts, then last year's
| 7000 series brought back the non-PRO Threadripper options.
| But even the entry-level Threadripper CPUs and TRX50
| motherboards available today are less affordable than HEDT
| systems were eg. 15 years ago. The high core counts
| available in mainstream desktop sockets have shifted the
| boundary between that segment and HEDT, and as a result
| there aren't good options to step up to a platform with
| more IO capability _without_ also stepping up to really
| high CPU core counts.
| dusted wrote:
| it just dawned on me how trivially simple it would be for memory
| controllers to implement ECC in UDIMMs, for every N words,
| reserve 1 word for parity. You gain ECC for a small decrease in
| capacity. Since the memory controller is on the CPU, it can
| easily abstract this away.
| kvemkon wrote:
| Indeed. Intel has recently implemented it in a low-cost CPU
| SoC: "in-band ECC".
|
| https://news.ycombinator.com/item?id=41090956
|
| But you not only loose some capacity. Some bandwidth is also
| lost. And perhaps even some CPU cycles, since likely in-band
| ECC hasn't been implemented purely in a hard IP-block.
| wtallis wrote:
| I think the bigger performance problem is that a read burst
| from one channel of RAM is no longer matched to the CPU cache
| line size when doing in-band ECC.
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(page generated 2024-11-17 23:01 UTC)