[HN Gopher] Broadwell's EDRAM: VCache Before VCache Was Cool
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       Broadwell's EDRAM: VCache Before VCache Was Cool
        
       Author : klelatti
       Score  : 50 points
       Date   : 2024-11-01 17:02 UTC (5 hours ago)
        
 (HTM) web link (chipsandcheese.com)
 (TXT) w3m dump (chipsandcheese.com)
        
       | pclmulqdq wrote:
       | EDRAM was very different, and IBM still uses it today. It is DRAM
       | that is on the same die as the cores, which makes it far slower
       | than AMD's VCache (which is SRAM). The concept is the same -
       | putting a huge amount of cache on chip - but it's a very
       | different solution.
       | 
       | The Intel solution was also not 3D stacked. It's a little like
       | having an HBM stack next to the chip as a cache.
        
         | jauntywundrkind wrote:
         | > _It is DRAM that is on the same die as the cores,_
         | 
         | From the article, it was actually a separate die/chiplets,
         | 
         | > _Broadwell implemented its L4 cache on a separate 77mm2 die,
         | creating a chiplet configuration. This cache die was codenamed
         | "Crystal Well", and was fabricated using the older 22nm
         | process._
         | 
         | A lot of interesting details in article about how widely
         | different this dram is, made to go fast fast fast. Fun read.
         | 
         | I'd really wanted a system with Crystal Well, seemed so cool. A
         | lot of macs seemed to have the Intel Iris Pro models that had
         | it. But general adoption in the PC market was - I feel - quite
         | poor.
        
           | pstrateman wrote:
           | I believe the high cache skus were Mac exclusive.
        
         | rbanffy wrote:
         | > and IBM still uses it today
         | 
         | On mainframes, z14's drawer controller (that controlled four
         | CPU sockets each) had a huge amount of eDRAM acting as an L4
         | cache for all cores in that drawer.
        
         | p_l wrote:
         | Late HP-PA cpus had 1T-SRAM chips used for L2 cache to provide
         | 32MB in PA-8800 and 64MB of L2 in PA-8900 (on top of still
         | large 768kB L1i and L1d)
        
       | rbanffy wrote:
       | "But I wonder if Intel could pull off high capacity caching
       | sometime in the future"
       | 
       | The Xeon Max processors had up to 64GB of HBM that could act as
       | memory or shadow external memory effectively acting like a huge
       | L4 cache.
       | 
       | No Xeon 6 seems to have that feature, at least not for now. Xeon
       | 6's top out at a paltry 504MBs of L3.
        
       | exmadscientist wrote:
       | It was, at least, pretty good for video gaming:
       | https://web.archive.org/web/20181025222235/https://techrepor...
       | though, alas, it doesn't look like the Wayback Machine properly
       | sucked up the whole article before the site got sold to
       | particularly nasty link/content farmers.
       | 
       | (I miss Tech Report.)
        
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       (page generated 2024-11-01 23:00 UTC)