[HN Gopher] Telum II at Hot Chips 2024: Mainframe with a Unique ...
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       Telum II at Hot Chips 2024: Mainframe with a Unique Caching
       Strategy
        
       Author : mfiguiere
       Score  : 22 points
       Date   : 2024-09-08 18:51 UTC (4 hours ago)
        
 (HTM) web link (chipsandcheese.com)
 (TXT) w3m dump (chipsandcheese.com)
        
       | _a_a_a_ wrote:
       | Seems very complex therefore very expensive (and possibly slow
       | where it matters, at L2). Or it might just work.
        
         | jauntywundrkind wrote:
         | On the contrary!
         | 
         | Yes there's a lot of cache. But rather than try to have a bunch
         | of cores reading each cache (sharing 96MB L3 for AMD's consumer
         | cores), now there's a lot of separate 36MB L2 caches.
         | 
         | (And yes, then again, some fancy protocols to create a virtual
         | L3 cache from these L2 caches. But less cache heirarchy & more
         | like networking. It still seems beautifully simpler in many
         | ways to me!)
        
       | jmclnx wrote:
       | To bad the mainframe business will not be spun off from IBM. Then
       | you may see innovation, but IBM see it as a cash cow.
        
         | wmf wrote:
         | Do the customers want innovation?
        
       | mikewarot wrote:
       | That's a huge amount of effort to let most of the transistors in
       | a computer (in the RAM) sit idle most of the time. Surely there
       | are viable non-Von Neuman alternatives that could be spun out
       | into general purpose computing.
        
       | tedunangst wrote:
       | I wonder what workloads would benefit from having an L4 victim
       | cache on another CPU, but that other CPU doesn't need its own L2
       | cache.
        
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       (page generated 2024-09-08 23:00 UTC)