[HN Gopher] Raspberry Pi Pico does line rate 100M Ethernet
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Raspberry Pi Pico does line rate 100M Ethernet
Author : rscott2049
Score : 166 points
Date : 2024-08-29 15:29 UTC (7 hours ago)
(HTM) web link (github.com)
(TXT) w3m dump (github.com)
| vardump wrote:
| Impressive.
|
| At first I thought it was the new Pico 2 (RP2350), but no, it's
| the old Pi Pico with RP2040.
| rscott2049 wrote:
| I expect the RP2350 to perform much better in this scenario! At
| the minimum, one of the DMA channels should be eliminated, and
| I'm hoping the CRC calculation will get faster.
| __michaelg wrote:
| > receive side uses a per-packet interrupt to finalize a received
| packet
|
| This has made much faster systems not being able to process
| packets at line speed. A classic was that standard Gigabit
| network cards and contemporary CPUs were not able to process VoIP
| packets (which are tiny) at line speed, while they could easily
| download files (which are basically MTU-sized packets) at line
| speed.
| crote wrote:
| Luckily the RP2040 has a dualcore CPU so one core can be
| dedicated entirely to receiving the interrupts, passing it to
| user code on the other core via a FIFO or whatever else you
| fancy.
| rscott2049 wrote:
| Fortunately, the receive ISR isn't cracking packets, just
| calculating a checksum and passing the packet on to LWIP. I
| wish there were two DMA sniffers, so that the checksum could be
| calculated by the DMA engine(s), as that's where a lot of
| processor time is spent (event with a table driven CRC
| routine).
| ghayes wrote:
| I just started playing around with PIO and DMA on a Pico, and
| it's really fun just how much you can do on the chip without
| invoking the main CPU. For context, PIO is a mini-language you
| can program at the edge of the chip that can directly respond to
| and write to external IO. DMA allows you to tell the chip to send
| a signal based on data in memory, and can be programmed to loop
| or interrupt to limit re-invoking. The linked repo uses these
| heavily for its fast Ethernet communication.
| stackghost wrote:
| For added clarity, the Pico includes an RP2040 which is where
| the PIO runs.
| ghayes wrote:
| Thanks, and you're correct; not sure why you got downvoted
| for this. For anyone curious here are the data sheets for
| RP2040 [for original Pico] and RP2350 [for Pico 2], which
| describe the systems in detail.
|
| RP2040: https://datasheets.raspberrypi.com/rp2040/rp2040-data
| sheet.p...
|
| RP2350: https://datasheets.raspberrypi.com/rp2350/rp2350-data
| sheet.p...
| SahAssar wrote:
| "the Pico includes an RP2040 which is where the PIO runs"
| to me sounds like it implies either
|
| - The original Pico was not built around the RP2040 as its
| central part ("includes" sounds to me like it was an
| addition)
|
| - The Pico 2 includes a RP2040 (in addition to the RP2350)
| which runs PIO
|
| Neither of which are true. I'm guessing some other people
| had a similar reaction.
| montecarl wrote:
| Why is the transfer rate non-linear with respect to the system
| clock? At 100 MHz the rate is 1.38 Mbit/s and at 200 Mhz it is
| 65.4 Mbit/s.
| vardump wrote:
| Maybe a lot of CRC errors or something. Just a guess.
| rscott2049 wrote:
| Wish I could answer that! All I can guess is that the slower
| processing speed creates a bottleneck in the LWIP stack
| somewhere...
| nyrikki wrote:
| Latency kills...and Ethernet uses exponential backoff.
| crote wrote:
| More specifically TCP uses exponential backoff. Ethernet will
| happily keep drowning you in packages at line rate, if I'm
| not mistaken.
| daymanstep wrote:
| CSMA/CD does use exponential back off, though I'm not sure
| if anyone is still using it.
| fach wrote:
| This is only for half-duplex ethernet communication so no
| one apart from some archaic systems.
| crote wrote:
| Very impressive!
|
| It would be interesting to see a short writeup of what kind of
| magic was required to achieve this, as there have been multiple
| failed attempts before this.
|
| I'm also curious about the performance boost from 2.81Mbit/link
| failure at 150MHz to 65.4Mbit/31.4Mbit at 200MHz. That doesn't
| sound like basic processor bottlenecks, but rather some kind of
| catastrophic breakdown at a lower level? Does it just
| occasionally completely fail to lock onto an incoming clock
| signal or something?
| molticrystal wrote:
| I see some examples that show this can be used as a lite http
| daemon.
|
| Is there enough room to have it control the ethernet port for
| another weaker or perhaps more powerful microcontroller?
|
| Can you combine multiple picos with one being the ethernet stack
| and another that modifies certain packets?
|
| Are there any other interesting things that can be done?
| bangaladore wrote:
| > Is there enough room to have it control the ethernet port for
| another weaker or perhaps more powerful microcontroller?
|
| Well there is a whole unused core and plenty of built in SRAM.
| Seems like a good way to have an open-source version of Wiznet
| chips [1]. It could support full protocol offloading like
| Wiznet's or a lower-level raw packet sender/receiver like the
| ENC424J600.
|
| [1] https://docs.wiznet.io/Product/iEthernet
| drones wrote:
| > Achieves 94.9 Mbit/sec when Pico is overclocked to 300 MHz, as
| measured by iperf
|
| Is this an effective rate, or just the reflection of a hardware
| limit?
| thetinguy wrote:
| Can it do 10BASE-T with no overclocking?
| crote wrote:
| Yes, see for example the project which this repo acknowledges
| at the end.[0]
|
| [0]: https://github.com/sandeepmistry/pico-rmii-ethernet
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(page generated 2024-08-29 23:00 UTC)