[HN Gopher] An FPGA built with 7400 series logic [video]
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       An FPGA built with 7400 series logic [video]
        
       Author : chrsw
       Score  : 97 points
       Date   : 2024-08-03 13:40 UTC (9 hours ago)
        
 (HTM) web link (media.ccc.de)
 (TXT) w3m dump (media.ccc.de)
        
       | djfergus wrote:
       | https://github.com/mnemocron/my-discrete-fpga
        
         | adrian_b wrote:
         | Very nice educational project, even if the main reason to use
         | an FPGA is to no longer have to deal with the limitations of
         | the 7400 series logic.
        
       | ComputerGuru wrote:
       | Full writeup (first in series, each post links to the next):
       | https://mnemocron.github.io/2023-12-08-DIY-FPGA-diary-0/
        
         | mikewarot wrote:
         | If you took _the right half of his CLB_ from his second
         | entry[1], and connected each input bit to one of it 's
         | neighbors, that's enough to have a computing fabric.
         | 
         | Latching them in 2 phase adds delay, but removes the need for
         | worry about timing, as it becomes known.
         | 
         | If you put 4 of them in parallel, so each neighbor gets it's
         | own output, it's a BitGrid[2,3], which I've been tinkering with
         | since the 1980s.
         | 
         | He referenced an earlier effort 2012 in his video[4,5] that
         | goes down the same detour towards computing fabrics. The HDL
         | for that fabric, _might_ prove useful for programming a
         | bitgrid.[6]
         | 
         | I see the appeal of routing fabric and saving silicon, and
         | especially wanting to keep the latency to bare minimum, but the
         | trade-offs aren't worth it in my opinion. Routing becomes a
         | nightmare, as does getting the timing of things right, and
         | watching out for race conditions.
         | 
         | If you give up and embrace latency, and the wasting of gates to
         | route signal, you end up with a homogenous, isolinear core.
         | (The same in any linear direction) You can rather easily shift
         | a part in any direction, rotate it, and flip it. You can route
         | around defective cells (assuming the shift register chain
         | doesn't break, of course). Latency goes to hell, but because
         | every single operation is pipelined, your throughput can go
         | through the roof, none of the data lines ever has to make it
         | all the way across the chip, except the clock signals. The
         | shift registers, and only have to load things before the
         | computing starts, so they don't have to be fast at all.
         | 
         | [1] https://mnemocron.github.io/2023-12-08-DIY-FPGA-diary-1/
         | 
         | [2] https://esolangs.org/wiki/Bitgrid
         | 
         | [3] https://github.com/mikewarot/Bitgrid
         | 
         | [4] https://hackaday.com/2012/11/01/discrete-fpga-will-
         | probably-...
         | 
         | [5]
         | https://web.archive.org/web/20150621104100/http://blog.notdo...
         | 
         | [6] https://github.com/Arachnid/dfpga/tree/master
        
           | convolvatron wrote:
           | seems like you could get pretty far bootstrapping a higher
           | level language. how far have people gotten?
        
             | bobsh wrote:
             | Not sure if this is quite the same idea, but
             | https://www.greenarraychips.com/ ?
        
               | mikewarot wrote:
               | No, but you could certainly use a GreenArray chip to
               | emulate a BitGrid faster than a normal embedded processor
               | could.
        
       | retrac wrote:
       | Back in the late 70s and 80s, many computers and other digital
       | systems were actually designed using basic blocks similar to
       | this. Since chip layout is by far the biggest expense (especially
       | back then) it made sense to design just one customizable chip,
       | and then produce it with different metal layers to configure it
       | into various arrangements, so it is relatively easily
       | "programmed" just before manufacturing. DEC's ill-fated VAX 9000
       | was done in this way, probably the last great pre-CMOS processor
       | design, with hundreds of ECL gate array chips all based on a
       | couple die patterns. Unfortunately the benefits of sheer density
       | from CMOS were undeniable. When they crammed the VAX into a $1000
       | CMOS microprocessor, it outperformed the $1 million VAX 9000 four
       | years later. These days it's relatively uncommon as a technique
       | except for rapid prototyping. With standard cell ASIC designs, a
       | gate array cell able to perform any function is still an option,
       | but modern design tools make it much easier to use more optimized
       | logic.
        
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