[HN Gopher] Standard cells: Looking at individual gates in the P...
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Standard cells: Looking at individual gates in the Pentium
processor
Author : todsacerdoti
Score : 67 points
Date : 2024-07-07 18:19 UTC (4 hours ago)
(HTM) web link (www.righto.com)
(TXT) w3m dump (www.righto.com)
| amelius wrote:
| Isn't modern EDA software sophiscated enough that it can place
| transistors as it sees fit, rather than rely on standard cells?
| frabert wrote:
| I don't think it's a software issue -- AIUI the issue is that
| foundries will only let you use blocks for which the process
| was tested, or the yields would be unreliable/all over the
| place
| quotemstr wrote:
| Really? I can't just call TSMC and say "Hey. Here's a mask.
| Please print 10,000, thanks."?
| morphle wrote:
| no, the mask must be made within the tight rules of the
| proprietary (and very secret) PDK of the TSMC Fab for that
| node. Just getting it certified that it fits the rules will
| cost millions.
|
| https://en.wikipedia.org/wiki/Process_design_kit
| quotemstr wrote:
| Are all fabs like this?
| hansihe wrote:
| It's probably more of a node thing than a fab thing. You
| would have a much easier time getting the fab to do
| random stuff for you on a legacy node compared to a
| leading edge node.
|
| Leading edge nodes are basically black magic and are
| right on the edge of working vs producing broken chips.
|
| You as a customer would never want to be in a position
| where you are solely responsible for yields.
| morphle wrote:
| There are only a few Fabs with nodes smaller than 28nm.
| Yes, all fabs are like that, with exception of a few
| experimental tiny labs at research institutes or
| universities.
| crote wrote:
| There are open-source PDKs[0] for education, research,
| and R&D - but they extremely rare and decades behind
| state-of-the-art.
|
| Nobody wants to give away trade secrets, so everything
| remains proprietary and behind an NDA until it has become
| completely obsolete.
|
| [0]: https://www.skywatertechnology.com/sky130-open-
| source-pdk/
| amelius wrote:
| Interesting. What is the granularity? Is it logic gates,
| or transistors?
| morphle wrote:
| the granularity is at all levels: standard cells
| (=gates), transistor shapes, metal layer shapes down to
| groups of atoms (for quantum dots).
| shrubble wrote:
| How were the Parallax Propeller guys able to do it? They
| have a Propeller2 that is in either 40nm or 28nm, IIRC.
| amelius wrote:
| Maybe in reality it is somewhere in-between, where TSMC
| says: here is a set of standard cells that we tested; you
| can use them but if you modify anything then it's at your
| own risk.
| morphle wrote:
| Maybe in therory, yes. In practise the fab will never
| allow you to do anything at your own risk because it
| might contaminate or break their $170 million machine. If
| you offer a few billion extra to cover that risk, your
| cheaper off building your own fab instead.
| amelius wrote:
| I'm not convinced that moving transistors around freely
| would break the machine. How could that possibly happen?
| morphle wrote:
| Going outside of the PDK rules you risk contamination
| because a chip machine is a high speed ultra-accurate
| automated mechanical and chemical laboratory. It sprays
| extremely corrosive acids and vaporizes metals. Going a
| nanometer outside of the rules would send droplet or
| flakes of chemicals flying around at high speed.
|
| https://www.epfl.ch/research/facilities/cmi/equipment/pho
| tol...
| haneefmubarak wrote:
| Think of it less like moving transistors around and more
| like moving small groups of atoms around (also, you can
| get single transistor cells for analog and power
| designs). The processes required to place the rough
| groups of atoms in roughly specific places involves
| extreme amounts of energy relative to the size of what
| you are working with, which is supplied in a combination
| of chemical, radiation, and thermal forms. As a result,
| predicting what additional effects attempting to form
| specific micro-shapes might have is nontrivial. They
| extensively simulate and then carefully test all of their
| approved cells on an ongoing basis. Deviating from this
| could cause unknown issues, including damage, but doing
| the necessary work to prequalify your custom cells would
| be prohibitively expensive for most applications.
|
| NB: this is obviously a simplified explanation.
| oasisaimlessly wrote:
| It wouldn't, except potentially for macro-level
| requirements like maintaining the correct fill ratio [1].
| Sibling comments are FUD.
|
| 1: https://semiengineering.com/knowledge_centers/material
| s/fill...
| kens wrote:
| I'm very skeptical of this too. I don't see a mechanism
| where moving transistors could break the machine.
| Although I wonder if you could blow up the die testing
| machine by making a chip that was one big charge pump :-)
| gary_0 wrote:
| It takes years just to figure out how to use the machines
| to produce actual working chips. They're the most
| specialized, intricate, expensive machines in the world.
| They're operated in enormous clean rooms that only allow
| for 1 half-micron sized particle per cubic foot. No fab
| is going to run them without exactly following the
| procedures they have spent billions developing and
| testing. They are also going to avoid potential delays as
| much as possible because these machines have to be
| running for as much of their useful life as possible to
| recoup the vast expense. The level of risk-averseness is
| insane, but warranted.
|
| If you haven't watched this video, I highly recommend it:
| _Indistinguishable From Magic: Manufacturing Modern
| Computer Chips_
| https://www.youtube.com/watch?v=NGFhc8R_uO4 It's a little
| outdated now, but very comprehensive and gives you an
| idea of how totally nuts the chip business is.
| morphle wrote:
| No. Actually, the state of the art of EDA software is worse.
|
| My project has been to design (and create) better EDA software
| that will simulate, optimize and therefore can form and place
| each individual transistor optimally to achieve lower power,
| higher speed and lower cost. There is only one drawback over
| all existing EDA software: my EDA tools must run on a ($100k)
| small supercomputer or FPGA cluster because it deals with a
| billionfold more transistors than existing EDA software and
| that takes more compute. It means my software is much cheaper
| than existing EDA software but will yield much better chips and
| wafers with much faster, better, cheaper and fewer transistors.
|
| A high level overview of my software is mentioned indirectly in
| my talk https://vimeo.com/731037615
|
| I'm eager to give a talk on my EDA software as well, please
| consider inviting me to give it?
|
| Other researchers and companies have proven that optimizing
| transistor design and placement over standard cell libraries
| and PDKs can be done, for example:
|
| https://www.micromagic.com/news/Ultra-Low-Power_PressRelease...
| was done with their own EDA software.
|
| I am very certain (but have no hard proof) that this is what
| Apple did on their M1, M2, M3. M4 and M5 processors, especially
| their high end M2 and M5 Ultra chips.
|
| What I'm claiming here is that humanity can design three to
| four orders of magnitude faster computer chips using at least
| two orders of magnitudes less energy making chips orders of
| magnitude cheaper if we only used better EDA software (CAD=>
| SYM=> FAB) that we use today. Moore's law is not at an end. I'd
| be happy to provide proof of this, but that takes a bit more
| effort than a HN comment.
| hansihe wrote:
| I don't know about this at any detailed level, but doesn't
| designing standard cells for leading edge nodes involve a lot
| of trial and error? Is a lot of the issues that can occur
| even well understood to the level that it can be simulated?
|
| With the approach you mention, would it involve creating
| "custom standard cells", or would the software allow
| placement of every transistor outside of even a standard cell
| grid? If the latter, I would have trouble believing it could
| be feasible with the order of magnitude of computing power we
| have available to us today.
| morphle wrote:
| The best results will be with custom shapes and custom
| individual placement of every transistor outside standard
| cell but within the PDK rules. Going outside the PDK rules
| will be even better but also harder.
|
| The trial and error you do mostly by simulating your
| transistors which you than validate by making the wafers.
| You can simulate with mathematical models (for example in
| SPICE) but you should eventually try to simulate at the
| molecular, the atom/electron/photon and even at the quantum
| level, but each finer grained simulation level will take
| orders of magnitude more compute resources.
|
| Chip quality is indeed limited by the magnitude of
| computing power and software: to design better
| (super)computer chips you need supercomputers.
|
| We designed a WSI (wafer scale integration) with a million
| core processors and terabytes of SRAM on a wafer with 45
| trillion transistors that we won't chip into chips. It
| would cost roughly $20K in mass production and would be the
| fastest cheapest desktop supercomputer to run my EDA
| software on so you could design even better transistors for
| the next step.
|
| We also designed a $800 WSI 180nm version with 16000 cores
| with the same transitors as the Pentium chip in the RightTo
| article.
| isotypic wrote:
| Has this WSI chip been taped out/verified? I must admit I
| am somewhat skeptical of TBs of SRAM, even at wafer scale
| integration. What would the power efficiency/cooling look
| like?
| morphle wrote:
| The full WSI with 10 billion transistors at 180nm has not
| been taped out yet, I need $100K investment for that.
| This has 16K processors and a few megabyte SRAM.
|
| I taped out 9 mm2 test chips to test transistors, the
| processors, programmable Morphle Logic and interconnects.
|
| The ultra-low power 3nm WSI with trillions of transistors
| anda Terabyte SRAM will draw a megaWatt and would melt
| the transistors. So we need to simulate the transitors
| better and lower to power to 2 to 3 terawatt.
|
| There is a youtube video of a teardown of the Cerebras
| WSI cooling system where they mention the cooling and
| power numbers. They also mention that they also modeled
| their WSI on their own supercomputer, their previous WSI.
| avnd wrote:
| That's a very ambitious project to say the least and I'll
| bite! Please elaborate
|
| Also, have you checked out the OpenROAD[1] project? It's a
| pretty impressive open source RTL to GDSII flow.
|
| I went to their most recent meetup at DAC'24 and there's a
| great community around the project.
|
| [1] https://theopenroadproject.org/
| morphle wrote:
| >Please elaborate
|
| I'd love to but what do you want me to elaborate on?
|
| We started making EDA tools and simulators (CAD, SYM FAB as
| Alan Kay says) and designing a wafer scale integration to
| run parallel Squeak Smalltalk (David Ungar's ROARVM) in
| 2007 and we are still working on it in 2024 so I estimate
| 30,000 hours now. I call that very ambitious too.
|
| >Also, have you checked out the OpenROAD[1] project? It's a
| pretty impressive
|
| No it is not pretty impressive EDA software, OpenROAD
| software quality is like Linux, " a budget of bad ideas" as
| Alan Kay typifies it. Openroad is decades old sequential
| program code, millions of lines of ancient C, C++ and bits
| of Python programs written in the very low level C
| language, riddled with bugs and pathes. The tools are
| bolted together with primitive scripts and very finicky
| configurations and parametric rules. Not that the
| commercial proprietary EDA software is any better, that
| usually is even worse but because you don't see the source
| code you can't see the underlying mess.
|
| Good EDA tools should be written by just a few expert
| programmers and scientists in just a few thousand lines of
| code and run on a supercomputer.
|
| So the first ambitous goal is to learn how to write better
| software (than the current dozens of millions of lines of
| EDA software code). Alan Kay explains how [1-3]:
|
| [1] https://www.youtube.com/watch?v=ubaX1Smg6pY
|
| [2] https://www.youtube.com/watch?v=Kj4fLRm2UC4
|
| [3] https://www.youtube.com/watch?v=1e8VZlPBx_0
|
| The second ambitous goal is to (learn to) design ultra low
| power transistor and free space optics. Learn from the best
| quantum physicists: [4].
|
| https://www.youtube.com/watch?v=-dQoImLNgWs
|
| The biggest problem is you need to get a couple of million
| investment just to test your software with a few tape-outs.
|
| I only managed to invest the money for the 30,000 hours of
| labour so far, you can guess how many millions that's
| worth.
| themoonisachees wrote:
| All tools at use in the last gen industry (40-12nm) currently
| make extensive use of standard cell librairies provided by
| foundries. I don't expect current gen nor next gen to change
| anything.
|
| Source: I work in EDA
| SuperscalarMeme wrote:
| I'll give you an alternate take: the compute power available to
| EDA software has been roughly scaling at the same rate as
| transistors on a die. So the complexity of the problem relative
| to compute power available has remained somewhat constant. So
| standard cell design remains an efficient method of reducing
| complexity of the problems EDA tools have to solve.
| Harmohit wrote:
| This is so cool! "Dissecting" a processor like this could be a
| fun educational activity to do in schools similar to dissecting a
| frog, but without the animal rights issues.
| kens wrote:
| Personally, I think everyone should try opening up a chip. It's
| easy (if the chip isn't in epoxy) and fun to look inside. You
| need a metallurgical microscope to examine the chip closely,
| but you can see interesting features even with the naked eye.
| Harmohit wrote:
| I didn't know there is such a thing as a metallurgical
| microscope. What makes them different from biological
| microscopes? And what is there primary purpose? I am assuming
| they don't make microscopes just for dissecting chips.
| _ihaque wrote:
| Biological microscopes illuminate the sample from below, as
| the samples are typically transparent. Metallurgical
| microscopes illuminate reflective samples from above.
|
| *"Below" meaning "on the opposite side from the objective"
| - you illuminate _through_ the sample.
| fest wrote:
| Metallurgical microscopes illuminate the sample "from the
| top side". The actual implementation even goes as far as
| making sure the illumination happens on the optical axis of
| the objective (as if the light was emitted from your
| eyes/camera, reflected from the sample and then seen by
| your eyes/camera). They are also called reflected light or
| epi-illumination microscopes.
|
| Biological microscopes, on the other hand illuminate the
| sample from the back side (which doesn't work for fully
| opaque objects).
| kens wrote:
| A regular biological microscope shines the light from
| below. This is good for looking at cells, but not so useful
| when looking at something opaque. A metallurgical
| microscope shines light from above, through the lens. They
| are used for examining metal samples, rocks, and other
| opaque things.
|
| An external light works for something like an inspection
| microscope. But as you increase the magnification, you need
| something like a metallurgical microscope that focuses the
| light where you are looking. Otherwise, the image gets
| dimmer and dimmer as you zoom in.
| userbinator wrote:
| Discarded RFID cards and the like provide a practically free
| source of minimally-encapsulated ICs, also often made on an
| old large process that's amenable to microscope examination.
| kens wrote:
| Having looked at a few RFID cards, there are a couple of
| problems. First, the dies are very, very small (the size of
| a grain of slat) so they are hard to manipulate and easy to
| lose. Second, the die is glued onto the antenna with gunk
| that obstructs most of the die. You can burn it off or
| dissolve it with sulfuric acid, but I haven't had success
| with more pleasant solvents.
| oldgradstudent wrote:
| > Intel started using automated place and route techniques for
| the 386 processor, since it was much faster than manual layout
| and dramatically reduced the number of errors. Placement was done
| with a program called Timberwolf, developed by a Berkeley grad
| student. As one member of the 386 team said, "If management had
| known that we were using a tool by some grad student as a key
| part of the methodology, they would never have let us use it."
|
| The grad student was Carl Sechen, advised by Alberto Sangiovanni-
| Vincentelli.
|
| https://ieeexplore.ieee.org/document/1052337
| casenmgreen wrote:
| I can't see any images.
|
| This is because of CloudFlare.
|
| When I go to the page, I get the CF "are you human" check, which
| I complete.
|
| However, every image load is also getting that check, but those
| checks are not presented to me - just the image doesn't load
| because a HTML page is being returned.
| immibis wrote:
| Ah, the Great Firewall of Corporate America.
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