[HN Gopher] Efinix Titanium Ti375 FPGA offers quad-core hardened...
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       Efinix Titanium Ti375 FPGA offers quad-core hardened RISC-V, PCIe
       Gen 4, 10GbE
        
       Author : mikhael
       Score  : 30 points
       Date   : 2024-03-23 16:51 UTC (6 hours ago)
        
 (HTM) web link (www.cnx-software.com)
 (TXT) w3m dump (www.cnx-software.com)
        
       | tverbeure wrote:
       | Looks like the 4 CPUs are hardened versions of the VexRiscv cores
       | that were already used as soft cores in their previous FPGA
       | product line.
       | 
       | If I had to design my own FPGA, I would probably make the same
       | choice. It's one of the best CPUs out there in terms of
       | area/performance/functionality and available under an MIT
       | license.
        
         | gleenn wrote:
         | What is the difference between a hard and soft core?
        
           | Rinzler89 wrote:
           | A hard-core is hardware baked into the silicone of the FPGA
           | from the fab in addition to the programable gates on board
           | and is therefore faster and more space and energy efficient,
           | soft-core is software synthesized from HDL code and programed
           | into the FPGA using its available gates, making it slower and
           | less eficient.
        
           | aseipp wrote:
           | "Hard" refers to components that are actually part of the
           | ASICs and exist on the die. For example, a "hard DDR memory
           | controller" means that there is a physical part of the die
           | that implements the DDR spec.
           | 
           | "Soft" refers to components that run on top of an FPGA. A
           | "Soft CPU" is a CPU that runs on the FPGA, and is not part of
           | the actual physical design.
        
       | jecel wrote:
       | It is interesting that the MIPI, PCIe and Serdes columns in the
       | table of device models is "-" for all of them. That is the case
       | for the other Titanium family and nothing is mentioned about
       | Serdes in the datasheet, only in the text description and table
       | for the whole family.
        
       | aappleby wrote:
       | It's an impressive pile of components on one chip, but the lack
       | of pricing and dev board info is annoying.
       | 
       | Anyone know if Efinix FPGAs have a decent tool chain?
        
         | aseipp wrote:
         | It's a traditional proprietary toolchain (about ~900MiB
         | .tar.gz) that uses Synplify for synthesis and a custom fork of
         | VPR for place and route, IIRC. It's reasonably easy to use and
         | most of the UI flow can be scripted by Python, too, which is
         | pretty nice. It's roughly comparable to something like Lattice
         | Radiant or Lattice Diamond in terms of scope and features,
         | IIRC, not Quartus/Vivado level.
         | 
         | I haven't updated my toolchain in a while so some of this may
         | be out of date.
        
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       (page generated 2024-03-23 23:01 UTC)