[HN Gopher] The Race to 2nm: RISC-V Chips in Japan - By Dr. Ian ...
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The Race to 2nm: RISC-V Chips in Japan - By Dr. Ian Cutress
Author : rbanffy
Score : 76 points
Date : 2024-03-07 16:48 UTC (6 hours ago)
(HTM) web link (morethanmoore.substack.com)
(TXT) w3m dump (morethanmoore.substack.com)
| blopp99 wrote:
| Love the substack name.
| moffkalast wrote:
| Now we just need another one named worththewirth about the
| merits of bloated software?
| tshanmu wrote:
| while it all sounds buzzwordy, as an chip industry outsider, none
| of it seems to make much sense.. is there an ELI5 version of
| this?
| Pet_Ant wrote:
| I mean you could paste into ChatGPT:
|
| > Please summarise https://morethanmoore.substack.com/p/the-
| race-to-2nm-risc-v-...
|
| But this is my _personal_ takeaway: there are companies
| building (or trying to) Risc-V cores at advanced geometries.
| That is somewhat unheard of for a rather new and not-yet
| popular core. This suggests a lot of momentum for it. It's
| actually a new Japanese company called "Rapidus" that has some
| major backers and it's working with Tenstorrent (which has had
| a lot of buzz over the last couple of years). So it's exciting
| because a new company is entering the ring, from a new country,
| and they are benefitting Risc-V which is gaining traction.
|
| There is another article on this here:
| https://www.anandtech.com/show/21281/tenstorrent-licenses-ri...
| tshanmu wrote:
| thanks!
| monocasa wrote:
| I'm pretty unclear as to the specifics. Rapidus is wafer
| processing and packaging; I get that. Is LSTC trying to create a
| fab directly, a fabless entity more or less directly developing
| chips, or just trying to be more like China's Big Fund, ie. a
| central point for disbursement of .gov money targeting domestic
| semiconductor R&D for other entities to consume as long as they
| march to the common drum?
| bloopernova wrote:
| https://en.wikipedia.org/wiki/2_nm_process
|
| I'm fascinated by the "Beyond 2nm" section, but don't really
| understand much of the terminology. If there are any industry
| experts reading, what sort of chip developments do you think will
| happen by 2030?
| morphle wrote:
| By 2030 we will have progressed to a few atoms per transistor
| in bulk CMOS, to wafer scale integration [3] and probably
| replaced most metal wires with free space optics [2]. We will
| see the first mass-manufactured SFQ [1] and RSFQ [4]
| superconducting Josephson junctions. Maybe we will see the
| first carbon nanotubes and superconducting circuits [5].
|
| [1] https://youtu.be/LUFp6sjKbkE?t=21701
|
| [2] https://www.youtube.com/watch?v=7hWWyuesmhs
|
| [3] https://vimeo.com/731037615
|
| [4] Rapid single flux quantum
| https://en.wikipedia.org/wiki/Rapid_single_flux_quantum
|
| [5] https://phys.org/news/2008-03-future-carbon-nanotubes-
| superc...
| wtallis wrote:
| Do you expect any of those to be in mass production six years
| from now?
| morphle wrote:
| That is literally the trillion dollar question.
|
| Will a Japanese or European company overtake ASML [1,2] in
| making bulk CMOS smaller?
|
| [1] https://www.asml.com/-/media/asml/files/investors/inves
| tor-d...
|
| [2] https://www.asml.com/-/media/asml/files/investors/inves
| tor-d...
| nsxwolf wrote:
| If "nm" is just marketing with no relationship to any feature
| sizes, what is a "race" to 2mm? Isn't it just the "race" to who
| decides to use the moniker first?
| wmf wrote:
| It is somewhat proportional to transistor density.
| xw390111 wrote:
| No.
|
| Every shrink, in theory, is supposed to mean you could have
| twice as many transistors per unit area. So although dimensions
| of transistors are similar from say 7nm to 5nm one should be
| able to pack twice as many in. And so when the foundry can
| double the transistor density, as measured over large areas, it
| gets to go to the next lowest number in the sequence. i.e.
| (7^2)/2 is roughly 5^2.
|
| You won't get that many, for lots of EE reasons, but in theory
| you could.
|
| It's also important to remember there are lots of things other
| than transistors in there. Contacts, wires, etc etc. and they
| have dimensions and packing requirements too. And if you can
| shrink or more tightly pack those things, transistor density
| also rises.
| caycep wrote:
| is Ian not writing for anandtech anymore?
| unixfg wrote:
| No, they've been mostly power supply and cpu cooler reviews for
| two years now.
|
| https://www.anandtech.com/show/17270/going-from-there-to-her...
| kergonath wrote:
| Which is a shame. I really miss the old articles by Anand,
| Andrei, and Ian and their in-depth discussions about CPU and
| SoC architecture. I haven't really found a consistent source
| to scratch that itch after they left.
| justinclift wrote:
| Have you seen: https://www.nextplatform.com ?
| brucehoult wrote:
| https://www.semianalysis.com/
|
| ?
| tux3 wrote:
| Chips & Cheese has some good CPU and SoC analysis
| barelyauser wrote:
| Why is he not employed at research? Semiconductor is a gigantic
| field growing by the year.
| vardump wrote:
| 2nm, sure, but what about SRAM register files and caches? SRAM
| has pretty much stopped scaling already.
|
| SRAM scaling is where I'd love to see some advances.
| xw390111 wrote:
| It's getting denser, but just not as fast as logic.
| https://www.techpowerup.com/309331/tsmc-n3-nodes-show-sram-s...
|
| You can make them smaller (like 20%) but those SRAMs suck
| electrically so no product actually uses them. So in actually
| shipping products the SRAM is roughly the same size (like 5%
| smaller).
|
| One needs to remember these things are drawn by algorithms (no
| one is by hand drawing billions of transistors) and there have
| been 20 years+ of advancements on the algorithms that draw SRAM
| and because of the regularity of SRAM there's more opportunity
| to pack.
|
| There's just not that much fat to cut in a SRAM structure
| (that's purely optimizing for density) so in many ways SRAM
| structures are the true measure of how small things are, and
| they are in fact used that way. And things are really really
| tiny already.
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