[HN Gopher] MRISC32 - An Open 32-Bit RISC/Vector ISA (Suitable f...
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       MRISC32 - An Open 32-Bit RISC/Vector ISA (Suitable for FPGA CPU)
        
       Author : peter_d_sherman
       Score  : 32 points
       Date   : 2024-01-17 19:09 UTC (3 hours ago)
        
 (HTM) web link (mrisc32.bitsnbites.eu)
 (TXT) w3m dump (mrisc32.bitsnbites.eu)
        
       | peter_d_sherman wrote:
       | Related:
       | 
       | Quake on an FPGA / MRISC32:
       | 
       | https://vimeo.com/901506667
       | 
       | https://news.ycombinator.com/item?id=39029529
        
       | system2 wrote:
       | 110MHz is not bad for quake. I remember playing with my Pentium
       | 100 back in the day. It looked so realistic like today's RTX with
       | some imagination.
        
       | ruslan wrote:
       | Is there GCC toolchain already for this ISA ?
       | 
       | Also, wonder how difficult would it be to add MMU to MC1 ?
        
         | snvzz wrote:
         | >gcc
         | 
         | There is a port. If you click on resources on the page's top
         | bar, it yields this page[0].
         | 
         | 0. https://mrisc32.bitsnbites.eu/resources.html
        
       | snvzz wrote:
       | >unfortunate design decisions
       | 
       | >(understood as pointed at a popular RISC architecture) lack of
       | addressing modes
       | 
       | Politely disagree. He should provide hard evidence (hard
       | numbers), as the authors of that ISA already did the research,
       | and came to a different conclusion, documented in the spec.
        
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       (page generated 2024-01-17 23:00 UTC)