[HN Gopher] How can I implement a simple asynchronous DRAM contr...
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       How can I implement a simple asynchronous DRAM controller? (2018)
        
       Author : peter_d_sherman
       Score  : 24 points
       Date   : 2023-11-10 07:25 UTC (15 hours ago)
        
 (HTM) web link (electronics.stackexchange.com)
 (TXT) w3m dump (electronics.stackexchange.com)
        
       | dmitrygr wrote:
       | Like this...
       | http://dmitry.gr/?r=05.Projects&proj=07.%20Linux%20on%208bit
        
         | 0xf00ff00f wrote:
         | Wow, pretty impressive project!
        
       | repelsteeltje wrote:
       | I'm confused. I understand very little about electronics, but it
       | seems the question was about asynchronous DRAM controller while
       | the XT and PET answers appear to describe a _synchronous_ setup?
       | 
       | Can someone explain?
        
         | celegans25 wrote:
         | The DRAM chips themselves are asynchronous (there's no clock
         | signal connected to the RAM chip), however they expect a
         | sequence of operations with specific timings in order to work.
         | The PET's solution was to create a small synchronous circuit to
         | generate the control signals with the correct timings for the
         | DRAM. This however wasn't the only way it could be done, as the
         | other answer states how the PC/XT did it with delay lines.
        
           | repelsteeltje wrote:
           | Thanks for this clear explanation
        
           | SomeoneFromCA wrote:
           | Apple 1 did it with single pulse RC, with timing constant of
           | 500 usec generators.
        
       | mk_stjames wrote:
       | This is a tangent, but in the first question post the OP mentions
       | considering implementing helper circuitry with quote "a GAL16V8
       | or something but I don't think I understand them well enough,
       | programmers are very expensive and the programming software is
       | closed source & Windows-only as far as I know."
       | 
       | I went down this path on a project a few years ago and I just
       | wanted to point out that you can burn the fuse file for the
       | Lattice GAL16v8 or GAL22v10 chips these days using a cheap TL866
       | Plus programmer...
       | 
       | And there is a very cool way to write the JEDEC fuse files- you
       | can draw out the circuitry you want using the [0] Digital
       | simulation package (it is similar to Logisim) and export a
       | compatible bitstream to burn from there. Thus skipping the need
       | to find a way to run the old WinCUPL or the even older DOS
       | program that was used to do the synthesis back in the day.
       | 
       | [0] https://github.com/hneemann/Digital
        
         | justtinker wrote:
         | Tried it on Windows 11 but got a Java run time error. Used the
         | recommended JRT https://adoptium.net/
         | 
         | Wandered through the https://github.com/hneemann/Digital site
         | and saw past issues with JRT but no obvious solution.
         | 
         | I have a couple hundred GALs of same or similar model number of
         | new old stock and was hoping to somehow make use of them.
        
       | dboreham wrote:
       | Weird seeing people do archeology on stuff I did almost every day
       | for a few years. Eventually I got a job at a company with clueful
       | CPU designers (Inmos) who had built in the DRAM timing generator
       | on-chip. It ran off the polyphase clock and was programmable so
       | the board only needed the address mux chips.
        
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       (page generated 2023-11-10 23:01 UTC)