[HN Gopher] How flip-flops are implemented in the Intel 8086 pro...
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How flip-flops are implemented in the Intel 8086 processor
Author : Tomte
Score : 76 points
Date : 2023-09-30 16:19 UTC (6 hours ago)
(HTM) web link (www.righto.com)
(TXT) w3m dump (www.righto.com)
| kens wrote:
| Author here for all your 8086 questions :-)
|
| By the way, HN's title editing makes the title appear a bit
| strange. Of course flip-flops are implemented in the processor.
| The article describes _how_ they are implemented.
| Tomte wrote:
| You're right, I edited the title. This HN misfeature regularly
| makes me furious.
| phkahler wrote:
| I've toyed with the idea of a flip-flop that captures the input
| on both rising and falling edges. Doing this at the gate level
| seems inefficient, so I've wondered if there is a better way to
| design it, and if anyone uses such a thing in production. What
| do you think?
| basementcat wrote:
| Double sided flip flops are used in DDR SDRAM and many other
| applications. https://docs.xilinx.com/r/en-US/am010-versal-
| selectio/Double...
| mochomocha wrote:
| I just wanted to express gratitude for the amazing work you're
| doing. As someone with no hardware background, I learnt a lot
| from reading your blog, and I marvel at the amount of
| collective human intelligence packed into all the tiny chips
| surrounding our daily lives.
| kens wrote:
| Thanks! Yes, it's amazing how much effort is packed into tiny
| chips, especially when you consider that the 8086 was 45
| years ago.
| denotational wrote:
| > However, the enable input is a fairly obscure feature for a
| flip-flop component; most flip-flop chips have a clock input, but
| not an enable.
|
| The clock-enable is actually _really_ common for flops in an
| integrated circuit; it might have been unusual in the days of
| discrete TTL, but as the article concedes, practically every cell
| library or FPGA fabric you can find will have it.
|
| Not only is it commonly present, but the CE is used all the time
| by the synthesis/technology-mapping process, indeed any time you
| write an `if` without an `else` within a clock-edge sensitive
| process, the tool is probably going to use a CE.
|
| On an FPGA, the only other option is a LUT-based feedback mux
| which can be undesirable for various reasons, including the use
| of additional routing resources if the fabric has no dedicated
| route in each CLB from the output flop to the input LUT, and the
| increased fanout on the flop.
| guepe wrote:
| Xilinx/amd fpga have a CE pin on many of its flops (if not
| all?). Not sure for altera/intel but would be surprised they
| wouldn't have.
| denotational wrote:
| I pretty much only work with Xilinx/AMD parts these days,
| and, at least on US/US+, they do indeed all have a CE on all
| the flops (unless there are undocumented degenerate cells
| with missing features).
| SomeoneFromCA wrote:
| Some observations:
|
| 1. Interesting, how fundamentally analog element such as
| capacitor, find its way into dynamic logic circuits.
|
| 2. The article states that asynchronous computers are not made
| anymore. Is not google TPU asynchronous?
| Tuna-Fish wrote:
| Nobody designs async things anymore, because they are much
| harder to validate, partly because there is no async equivalent
| of all the tooling used to validate synchronous logic. The
| final product might be better, but if it takes 3 years longer
| to ship because validation is harder, there is no room for it
| in the market. (Because the synchronous competitor has already
| shipped their next version on a better process node by the time
| you get yours out.)
| dekhn wrote:
| All digital logic is fundamentally analog.
|
| No, the TPU is not async. It has a single main clock. It does
| work in parallel, but it's still synchronously clocked. As neat
| as async is, it's truly a paradigm shift that affects nearly
| everything about your system and most of us can'd think in
| partial differential equations.
| kens wrote:
| One of Vonada's 14 engineering maxims is "Digital circuits
| are made from analog parts." That said, dynamic logic that
| depends on capacitance is more analog than most digital logic
| :-)
|
| Vonada's engineering maxims:
| https://twitter.com/kenshirriff/status/1633154548318732289
| dekhn wrote:
| OK I learned a bit today- I didn't realize transistors were
| considered "active", or that dynamic logic was uncommon.
|
| Vonada's engineering maxims are pretty scary to me- an
| amateur hobbyist soldering various chips together to build
| simple projects like "a rotary encoding controlling a
| binary counter visualized with LEDs". I spend many hours
| soldering and carefully debugging every individual
| component, and when I integrate, spend many more hours
| debugging why something doesn't work. The failures are
| almost always because I did something dumb, like wiring up
| VCC and GND backward, I honestly don't know that I'd be
| able to debug "When all but one wire in a group of wires
| switch, that one will switch also." in my binary counter's
| inputs or outputs.
| tzs wrote:
| > Vonada's engineering maxims are pretty scary to me- an
| amateur hobbyist soldering various chips together to
| build simple projects like "a rotary encoding controlling
| a binary counter visualized with LEDs"
|
| Fortunately for probably most hobby projects you don't
| have to worry about most of those things.
|
| A lot of those maxims concern failures of the lumped
| element model.
|
| The lumped element model is a model where all the
| capacitance occurs in capacitors, all the resistance is
| in resistors, all the inductance is in inductors, and so
| on, and wires are zero resistance conductors of current
| that do not couple magnetically or inductively with
| anything.
|
| If clock speeds aren't too high, there is enough gap
| between the highest 0 logic voltage and the lowest 1
| logic voltage, wires aren't too long, voltages and
| currents aren't too high or too low, and you don't do
| anything like put loops in your wires (other than when
| you are intentionally trying to make an inductor) the
| deviations of reality from the lumped element model
| shouldn't cause any problems.
|
| As you deal with higher frequencies reality starts to
| noticeably diverge from the lumped element model. You
| have to start worrying about things like capacitance
| between leads on your components, inductance between
| wires, and wires acting like transmission lines.
|
| Keep going up in frequency and you can get to a point
| where you have to use software that can solve (exactly or
| numerically) Maxwell's equations for the fields around
| things and take into account interactions with those
| fields.
|
| Hobbyist projects can do things that get past where the
| lumped element model is all you need, such as WiFi or
| Bluetooth which operate at several GHz, but usually those
| functions are handled by modules that the hobbyist buys
| that are (hopefully!) designed by people who know how to
| deal with high frequencies. E.g., you buy an RF module
| that does the scary radio stuff, and you control it from
| a microcontroller that is running an order of magnitude
| or more slower than the RF module, and whatever inputs
| and sensors and non-radio outputs you have are probably
| at least an order of magnitude slower than your
| microcontroller.
|
| Those non-RF parts of the project are likely to be well
| in the realm where lumped element works.
|
| Most of the rest of the maxims concern things that are
| mostly going to be a problem for big projects where you
| might be worrying about things like synchronizing things
| across dozens of subsystems and with very tight
| tolerances.
| dfox wrote:
| In digital circuits the "frequency" when the lumped model
| breaks down is determined by the slew-rate (ie. spectral
| content of the edges), not the bitrate/clock frequency.
| In the electronics hobbyist community there are many
| cases when you can run into that issue head first while
| just connecting modules together (because the whatever IC
| on the module has significantly faster slew-rate than you
| need). Another example are MCUs with somewhat high
| internal clock rates and their power requirements, even
| 20-ish year old dsPIC requires somewhat involved supply
| decoupling topology to work at all (and the quality of
| decoupling for ESP32 has direct effect on signal quality
| and how much of RF noise it spews out).
| dfox wrote:
| > I honestly don't know that I'd be able to debug "When
| all but one wire in a group of wires switch, that one
| will switch also." in my binary counter's inputs or
| outputs.
|
| The intention of the maxim is to design the system in a
| such way that the all-but-one situation never happens.
| And if it has to happen then you need to be sure that the
| "analog stuff" and "black magic" like power supply
| decoupling and ground return paths is handled correctly.
|
| And in fact the binary counter is perfect example for
| that. You can design that as an ripple counter or
| synchronous counter. Ripple counter is simpler and does
| not suffer from these kind of issues because the
| switching ripples through the bits LSB to HSB, which also
| means that there is a period of time before the output
| stabilizes where it is simply wrong, which is the main
| drawback of that design.
| SomeoneFromCA wrote:
| No one argues, that digital logic is indeed analoh, however
| you rarely see reliance on a passive element (in analog
| sense), to be "active" in a digital sense. DRAM is the only
| widely known example.
| duskwuff wrote:
| > you rarely see reliance on a passive element (in analog
| sense), to be "active" in a digital sense
|
| This technique is referred to as "dynamic logic". It was
| common in the early days of MOS ICs -- for instance, it was
| used extensively in the original 6502 -- and still finds
| some usage in high-performance ICs.
| dreamcompiler wrote:
| It's only because capacitors let you use fewer transistors.
| Any effort to shrink memory cells as much as possible
| inevitably leads to a capacitor-transistor hybrid solution.
|
| In logic circuits class they don't talk about areal
| constraints, but IC designers have to think about such
| things.
| elromulous wrote:
| In VLSI you pay a lot of attention to those capacitances. I've
| even designed some VLSI circuits that make intentional use of
| those capacitances.
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