[HN Gopher] SiFive's P870 Takes RISC-V Further
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SiFive's P870 Takes RISC-V Further
Author : zdw
Score : 113 points
Date : 2023-09-04 03:47 UTC (19 hours ago)
(HTM) web link (chipsandcheese.com)
(TXT) w3m dump (chipsandcheese.com)
| camel-cdr wrote:
| > An insane programmer can set LMUL to a value higher than 1,
| making vector instructions address contiguous blocks of
| registers.
|
| I hope that most code won't use LMUL=1, but LMUL>=1 when
| possible, otherwise we'd leave performance on the table.
|
| The only case I can currently fore see where using LMUL=1 and
| manually unrolling instead will likely be always beneficial is
| vrgather operations that don't need to cross between registers in
| a register group (e.g. byte swapping).
|
| > As with all new architectural features, we'll have to wait and
| see how useful RISC-V's LMUL will be.
|
| RVV without LMUL would be a lot worse, the entire extension is
| build around the LMUL concept and it's really nice to work with
| imo.
| dsharlet wrote:
| > The only case I can currently fore see where using LMUL=1 and
| manually unrolling instead will likely be always beneficial is
| vrgather operations that don't need to cross between registers
| in a register group (e.g. byte swapping).
|
| What about algorithms where register pressure is an issue?
|
| I think the problem with LMUL is it assumes that you always
| want to unroll the innermost dimension (where the vector loads
| are stride 1). That's usually, the _last_ dimension I try to
| unroll, if there are any registers left over. If there is any
| sharing of data across any other dimension in the algorithm, it
| 's better to tile/unroll those first.
|
| Of course, for a simple algorithm, there will be registers left
| over. But I think more interesting algorithms will struggle on
| RVV if you _must_ use LMUL > 1 for performance.
| camel-cdr wrote:
| > What about algorithms where register pressure is an issue
|
| Then you'll probably saturate the processor without using a
| larger LMUL, but I think many algorithms can work with
| LMUL=2, without running out of registers.
| OhMeadhbh wrote:
| I'm bullish on RISC-V, but sort of bearish on SiFive. The last
| _several_ systems I 've used have been StarFive systems (which is
| distinct from SiFive.) They (SiFive) seem to be more of a custom
| IP shop, where you go when you want to spin some custom silicon
| but not pay ARM. But now that we've broken with China re: chip
| production, is there anyone on this side of the pacific I can get
| catalog parts from?
|
| So... their cores are great, but if I'm only going to see them if
| I write a very large check to SiFive, they're sort of irrelevant
| to my world. I would love to have SiFive IP that _doesn 't_ use
| Rocket/Scala/Chisel and _does_ produce catalog parts.
|
| That could be just me. I enjoy getting my hands dirty.
| eigenform wrote:
| I'm curious what your objections to Chisel are! (I don't really
| care for Scala either)
| pama wrote:
| Is there any good benchmark/comparison of the current risk-v
| boards for use in hobby projects?
| ChuckMcM wrote:
| The ugly truth though is that "catalog parts" carry with it a
| whole boatload of overhead in the form of sockets/memory
| infrastructure/voltage regulators/cooling standards etc. The
| current "big money" is in being the core that gets integrated
| into a phone or tablet. It makes me sad too as this is a pretty
| spiffy micro-architecture to play around with.
| fidotron wrote:
| I agree with this, and suspect that if SiFive did get big
| enough they would start creating patented extensions as a
| defensive strategy.
|
| Personally I'm more curious about RISC-V in tiny
| microcontrollers, and were I guiding semiconductor strategy I'd
| be way more concerned about ability to build embedded systems
| than GPU farms. The ecosystem to do the former can evolve into
| the latter, but skipping to the end is just a route to burn
| absolutely billions.
| OhMeadhbh wrote:
| FWIW, after listening to Chuck Peddle's CHM Oral History
| interview, I sort of realized I didn't need the ARM ecosystem
| and just designed my own 6-bit microcontroller. Granted, I'm
| only doing some very simple control applications and fabbing
| at 800nm, so it's not going to be competing with an i7 or an
| A72 anytime soon.
|
| IIRC, the RISC-V spec includes an "embedded profile" that
| specifies a CPU with 16 32-bit registers, so that should make
| RV32 even smaller than it would be otherwise. SiFive designed
| a dog-simple 2-stage pipeline 32 bit core that could even run
| without I-cache. I mean, it's not a speed demon, but it was
| implementable in many fewer gates than their earlier E cores.
|
| I worked at SiFive for a year and couldn't make sense of
| their product strategy. But maybe that's a me problem and not
| a SiFive problem.
|
| I really do sort of wonder what they're doing with 175m in
| Series F funding. Where do you go from there?
| photonbeam wrote:
| Presumably lots of runway for salaries until next funding
| round or exit event
| fidotron wrote:
| I don't think it's you.
|
| The only true thing that could be done is to have some top
| secret insight into CPU design optimization and apply it to
| RISC-V guiding the actual open spec along with you as
| necessary. Which is close to what Apple appear to have done
| with ARM64, but then Apple did hire/acquire an absolutely
| incredible team to get them there, and have the money to
| reward them.
| taway32r41 wrote:
| Here's a class at MIT that takes undergraduates who don't
| even know verilog and at then end of the class they have a
| mostly passable RV32I. Admittedly pushing that through VLSI
| CAD will not be push-button easy but many universities also
| have an undergraduate tape-out class, including MIT...
|
| https://ocw.mit.edu/courses/6-004-computation-structures-
| spr...
|
| Via MPW and assembly service one can easily have that die
| manufactured, packaged and mounted on custom PCBs for under
| $50K, a.k.a. much less than you'll pay in salary to have it
| designed, fabricated and tested. Even at non-American labor
| rates.
|
| In 2023 producing a computing core, albeit not a state-of-
| the-art one, is just not the moat it once was...
| imtringued wrote:
| > SiFive designed a dog-simple 2-stage pipeline 32 bit core
| that could even run without I-cache. I mean, it's not a
| speed demon, but it was implementable in many fewer gates
| than their earlier E cores.
|
| How about SERV... That core can be configured to not use a
| register file (everything stored in BRAM).
| panick21_ wrote:
| RISC-V will not do X and then Y. RISC-V is going in all
| directions at the same time. People are pushing to the
| smallest micro controlers, to data centers and to niche
| applications like space all at the same time.
| photonbeam wrote:
| You normally only see ARM when you cut a big check too, they
| sell IP that others get fab'd
| OhMeadhbh wrote:
| Well... our ARM cores use more standard tooling. I sort of
| detest System Verilog, but I detest it a lot less than
| Rocket/Chisel. And as annoying as it is to write a big check
| to ARM, at least you can hire people who know how to use your
| IP.
|
| It probably wasn't obvious from my earlier comment, but I was
| comparing SiFive to ARM and then I was comparing SiFive with
| other RISC-V IP vendors (and open source projects.)
| rwmj wrote:
| They seem to be positioning themselves as the "RISC-V Arm"
| equivalent. Of course there are significant differences, like
| they don't completely control the architecture (as Arm does).
| But Arm have made a decent business out of it, so SiFive should
| be able to do the same.
|
| By the way StarFive were SiFive China until SiFive divested
| them (the split was a bit acrimonious).
| qwytw wrote:
| > But Arm have made a decent business
|
| ARM is making peanuts compared pretty much all the companies
| that actually make high-end chips. Their IP seems to be worth
| much more than the business.
| rwmj wrote:
| Just because Arm isn't huge, it's still not nothing.
| They're about to go into a floatation to try to raise
| $50-55 billion, which is not too shabby! (Even if it's down
| from the original target of over $60b).
| qwytw wrote:
| True (assuming the stock price doesen't crash immediately
| after the IPO) but still it's not really justifiable
| based on their current financial figures or future growth
| prospects.
|
| I'm not even sure what the valuation this valuation might
| even be based on (which admittedly applies to a bunch of
| other companies which actually end up doing quite well).
| They might conceivably be worth 100 P/E as an acquisition
| but an IPO would only make it less likely?
|
| $50-55 billion would mean that ARM is more overvalued
| than Nvidia and Nvidia actually has a realistic chance to
| grow into that valuation.
| fidotron wrote:
| It is worth considering why you expect anyone else could be
| more successful.
|
| On the one hand you have ARM investors wanting them to
| extract more revenue, and the ARM customers do not want to
| pay more or have more restrictive licenses. They are in a
| bit of a nasty equilibrium but one that will hit all IP
| companies eventually.
|
| An old colleague of mine has got into the idea businesses
| are now going to put the big squeeze on all suppliers that
| count as part of gross margins, which would include ARM,
| while essentially ignoring operational costs. The
| implication would be companies looking to use RISC-V would
| be more inclined to pay chip design houses on a contract
| basis more upfront than have anything including royalties.
| I dislike the idea but think he is right, and that the
| future of electronics is about to go through the same sea
| change that software did with open source and the emergence
| of SaaS.
| OhMeadhbh wrote:
| Well. They effectively control the architecture. All the
| technical committees in the foundation report up through one
| of the three principals at SiFive. I can't imagine a
| technical spec would be published without the consent of
| SiFive.
| vintermann wrote:
| > the split was a bit acrimonious
|
| That's another thing they have in common with Arm.
| Fordec wrote:
| If RISC-V is just their platform to provide a different
| company to license IP from, I'm just sticking to Arm.
|
| RISC-V is only interesting as a platform for a _different_
| business model.
| imtringued wrote:
| Jim Keller's Tenstorrent worked with SiFive instead,
| because ARM didn't want to customize their cores for
| machine learning workloads and now they are developing a
| RISC-V with a ridiculous performance profile.
| rwmj wrote:
| For sure, but I guess you're not in SiFive's target market.
| You're not a customer of Arm either, unless you are
| licensing chip designs from Arm. Someone who merely buys
| Arm chips is a customer of the company that licenses from
| Arm, not of Arm.
|
| Nevertheless it seems plausible there are companies that
| would like to license a RISC-V design (rather than
| implement their own or use one of the slower free cores)
| and might therefore be a SiFive customer. I'm not saying
| it's going to be a huge market, probably a much smaller one
| even than Arm, but it's a possible one.
| [deleted]
| crote wrote:
| The biggest benefit of RISC-V is that you are not married
| to a single IP vendor.
|
| If ARM decides to change their license terms, you are
| screwed. If SiFive decides to change their license terms,
| you could just switch to a competing IP vendor without any
| changes to your software ecosystem.
| OhMeadhbh wrote:
| ARM seems to be half-way moving in this direction. They
| allowed "royalty free" licenses to educational
| institutions for some of their low end M0/3/4 cores. But
| yeah, I think you're right. The cool thing about RISC-V
| is you can just pick up the ISA and run with it. I'm
| pretty sure the Rocket core generator is released under a
| BSD license. SiFive sort of makes sense if you want to
| integrate proprietary IP with open IP, and some people do
| actually want to do that. I don't know if there's enough
| demand for that, though.
|
| But yeah. Even though we have compilers, it's not like
| you can spin up support for a new ISA in the drop of a
| hat. If you launched a project with a StarFive part and
| then decided you wanted to use SiFive IP, you should be
| able to use the same tooling. The impact of that
| shouldn't be under-estimated.
| RetroTechie wrote:
| That's an important advantage: go Arm, and ultimately
| you'll be dealing with Arm (the IP licensing company), or
| with a 3rd party which deals with them.
|
| Go x86, and you'll end up dealing with Intel, or AMD
| (okay, there's Via & _maybe_ a few makers of legacy x86
| parts).
|
| Go RISC-V, and roll your own or pick from a growing list
| of vendors, are both valid options. And switch supplier
| while keeping your toolchain ecosystem.
|
| I'd expect _at least_ that this will spur innovation in
| the field. Likely increase consumer choice.
|
| More suppliers of [insert product type here] is almost
| always a good thing.
| yuumei wrote:
| Just a warning to anyone thinking of using the sifive boards
| https://forums.sifive.com/t/unmatched-boot-issues/6236
| [deleted]
| greggsy wrote:
| This just suggests that one board has an undiagnosed issue? Is
| there some other insight I'm missing?
| synergy20 wrote:
| SiFive is now a IP license shop I think? similar to Andes from
| Taiwan who also sells RISC-V cores. Difference is that SiFive is
| more on the desktop CPU while Andes is more on the embedded
| space.
|
| In the Machine Learning startup field, RISC-V is the most popular
| choice these days.
|
| RISC-V also becomes a national priority for China as far as I can
| tell, it won't surprise me the best RISC-V designs will be from
| there.
| phkahler wrote:
| We still need a an open and free GPU to pair with this in a SoC.
| marcodiego wrote:
| Hantro and panfrost fill this gap. No blob is required afaik.
| MobiusHorizons wrote:
| While very cool, open source drivers for propriety a
| proprietary gpu design is not quite the same as open silicon
| or open gpu isa, which is what I think the parent was asking
| for.
| 0xDEF wrote:
| This is not an open and free CPU. It just implements the open
| and free RISC-V instruction set. Judging by the SiFive business
| model they will in the future inevitably add proprietary
| extensions.
| [deleted]
| sylware wrote:
| We will need some sort of soft tablesheet in order to know how to
| write assembly to leverage instruction fusion in a best effort
| fashion.
|
| I wonder how many GHz this uArch would reach with TSMC 3nm.
| brucethemoose2 wrote:
| Tenstorrent has an 8-wide RISC-V core available for licensing:
|
| https://tenstorrent.com/risc-v/
|
| ...But I am starting to get suspicious of Tenstorrent. Maybe they
| have some customers using their designs privately, but I never
| see _any_ of their hardware used in public.
| ireallywantthat wrote:
| Sorry for my ignorance, but any idea when we can see Desktop
| Processors powered by RISC-V architecture? It would be breath of
| fresh air to see new architectures power the desktops.
| tremon wrote:
| https://www.crowdsupply.com/milkv/milk-v-pioneer
|
| Also pioneer pricing, as can be expected. But it has uATX form
| factor, ddr4, pcie3, usb3, sata3 connectivity. You could
| certainly build a nice desktop with it.
| AlotOfReading wrote:
| You can buy a RISCV SBC and run a Linux desktop on it today.
| It's just not competitive with x86 in performance or software
| support. The closest you'll get to that outside arm or x86 is
| Talos II stuff, which runs PowerNV.
| marcodiego wrote:
| I remember this one: https://abopen.com/news/building-a-risc-v-
| pc/ . Since it is from 2019, it is likely there have been some
| advancements. I also hope for a riscv desktop; it could even be
| ryf certifiable.
| crote wrote:
| The HiFive Pro P550 should be available this summer, for a
| pretty desktop-like experience. Don't expect RISV-V to directly
| compete with Intel/AMD on the high end for at least another
| decade, though.
| snvzz wrote:
| >Don't expect RISV-V to directly compete with Intel/AMD on
| the high end for at least another decade
|
| Actually 2024.
|
| SiFive P870, Tenstorrent Ascalon, SOPHON SG2044, Ventana
| Veyron, and more.
| rwmj wrote:
| Rivos too ...
| snvzz wrote:
| Rivos hasn't announced anything. There's several other
| companies we know are working on processors but haven't
| announced a thing.
| therealcamino wrote:
| If we're being generous/technically correct (which of course
| is the best kind of correct), on September 3rd they've got
| about two and a half weeks left to meet "this summer".
| Informally, most people would expect that to mean
| June/July/August.
|
| I haven't seen any news on since January, and no concrete
| shipping date. I signed up on the announcement email list and
| haven't seen anything there either (or at least I think I
| signed up; I don't even see an acknowledgement email.)
|
| That's not really a criticism or doomsaying about Intel or
| SiFive from me -- I'm really interested to see what they have
| -- but they could do with a better communication strategy.
| rwmj wrote:
| Sophgo sells some: https://www.tomshardware.com/news/milk-v-
| offers-a-trio-of-ri...
| blacklion wrote:
| I'm in market to replace platform for my home-built NAS. I'm
| looking at EPYCs 7001 or 7002 with SuperMicro platform
| (second hand) as primary target.
|
| When I seen this Milk-V Pioneer platform I was very
| enthusiastic: looks like what I need (minus IPMI, but I can
| omit this requirement) - one slot for 10G network, one slot
| for HBA, M.2 slots for caches, I can select RAM (in opposite
| to most of these platforms, where RAM is soledrid-on), plus
| ability to experiment with new platform. Looks perfect.
|
| But... $1499?! Plus VAT to import to Europe?!
|
| Sorry. I pass :-(
|
| Why does it cost SO MUCH!?
| rwmj wrote:
| Because it's a development platform, produced in small
| quantities. It also has 64 cores which I guess an EPYC
| doesn't have at that kind of price.
| blacklion wrote:
| On one hand I agree with you. It is apples-to-oranges to
| compare new development platform and old, second-hand,
| production one.
|
| On other hand... There is NO comparable production RISC-V
| platforms. You say "It has 64 cores" - well, it is good
| argument when there is choice. But there is no choice on
| RISC-V side, there is no such platform with 32 or 8 or
| any other number of cores. So, I compare what I can buy
| with "RISC-V" badge and what I can buy with "amd64"
| badge. When I choose EPYC I could choose from 8 cores up
| to 64 cores, according to my wallet and needs. For 1000
| euro I could have good, proven MoBo which offers more
| than this "development platform" (i.e. IPMI and VGA exit,
| which means I don't need any videocard to occupy so
| precious PCIe slot - and I think, it is good idea for
| DEVELOPMENT platform to have full remote control &
| access, IPMI or some other) and 8 core/16 threads first
| generation EPYC (which will be faster core-to-core, I'm
| sure), NEW. If I agree to buy second-hand hardware it
| will be about 550 euros (same mobo, same CPU). For 1400
| euros I will get NEW 16 cores / 32 thread EPYC + mobo
| combo, or about 700 euros second-hand.
|
| Yes, I know, development vs. production, but this
| situation stays the same for years now.
|
| BTW, situation is the same with ARM platforms too - there
| is no way to buy "big desktop/small-server class" ARMv8
| board with good set of expansion slot.
| zahllos wrote:
| Because it won't sell in anywhere near the volumes
| comparable x86 motherboards will.
|
| It's the same for the Talos II using IBM's POWER. It costs
| a lot because a) it is designed as a workstation and b) the
| volume just isn't there.
|
| Economies of scale basically.
| loudmax wrote:
| You can get RISC-V based single board computers today.
|
| I think the meaningful question is when we'll see RISC-V CPUs
| that are performance competitive with x86 or ARM CPUs. In that
| case, probably not in the near future, at least not for several
| years at least. x86 and Arm CPUs have decades of optimization
| behind them. That's the CPU designs themselves, and also
| compilers, etc. RISC-V has a lot of catching up to do, and Arm
| and x86 aren't static targets.
|
| That isn't to say that RISC-V _won 't_ catch up. There's real
| momentum behind RISC-V. Also, the development of software built
| using machine learning introduces wildcards and the possibility
| of disruption. So in the medium to long term (end of the
| decade, maybe?) we might see interesting cell phones or laptops
| that are useful for more than Hacker News tinkerers. I'm
| looking forward to them.
| intrasight wrote:
| We need to to keep a competitive landscape.
|
| >when we'll see RISC-V CPUs that are performance competitive
|
| As you said, Arm and x86 aren't static targets. So while
| they'll catch up to where Arm is today, Arm will be somewhere
| further ahead at that point. Especially as implemented by
| Apple silicon. My concern remains that Apple will have to
| investment strength to always be a few years in the front.
| Their lead could in fact increase. And that's just CPU.
| [deleted]
| rollcat wrote:
| https://drewdevault.com/2022/01/15/2022-01-15-The-RISC-V-exp...
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