[HN Gopher] A close look at the 8086 processor's bus hold circuitry
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A close look at the 8086 processor's bus hold circuitry
Author : Tomte
Score : 41 points
Date : 2023-08-05 17:39 UTC (5 hours ago)
(HTM) web link (www.righto.com)
(TXT) w3m dump (www.righto.com)
| h2odragon wrote:
| > Much of the complexity is probably due to the wildly different
| behavior of the pins between minimum and maximum mode.
|
| That truly does seem to be a silly design (as does the pin count
| constraint that "excuses" it). "Gakulicious engineering by intel"
| could probably fill a decent textbook.
|
| What else might've used this? 8087 doesn't seem like enough of a
| thing to justify an entire separated bus like this, were they
| thinking multiprocessor uses? were there any? "asymmetric
| multiprocessing" i guess it'd have to have been.
| peterfirefly wrote:
| >were they thinking multiprocessor uses? were there any?
| "asymmetric multiprocessing" i guess it'd have to have been.
|
| https://en.wikipedia.org/wiki/Intel_8089
|
| As for pin count, google around a bit and find out how much
| trouble the relaxed attitude to pin count caused for Motorola.
| The 68K paid dearly for its many pins.
| kens wrote:
| Yes, Intel had pointless restraints on pin counts; the 8008
| processor was barely allowed 18 pins. So the 8080 designers
| were lucky that they got all the way to 40 pins. Federico
| Faggin has ranted about this in a few places.
|
| As far as applications of the bus, multiprocessing was a big
| motivation. Intel had big plans with their Multibus. Intel had
| more plans for coprocessors as well. They introduced the 8089
| I/O coprocessor to provide mainframe-style channel I/O, but it
| wasn't very popular.
| h2odragon wrote:
| had to go refresh my memory on the 8089; here's a manual in
| case anyone else is curious. Its fun.
|
| http://bitsavers.org/pdf/intel/ISIS_II/9800938-01_8089_Assem.
| ..
| ggeorgovassilis wrote:
| More pins means more soldering when planting the chip on a
| mainboard (even if sockets are used, they need to be
| soldered, too) which increases time, cost and chances that
| something goes wrong and the entire mainboard must be
| discarded.
| monocasa wrote:
| Yeah, but that's a balance like everything else. It's far
| too easy to end up somewhere where the complete design
| requires added complexity to figure out the state of the
| multipurposed pins (and that associated logic's additional
| pin count) that you end up with a harder to manufacture
| product.
| bogantech wrote:
| Through-hole components would be wave soldered not done by
| hand - so no, time and reliability have nothing to do with
| it.
|
| Just about any manufacturer would be reworking boards that
| failed QA not throwing them away.
| amelius wrote:
| I'm getting flashbacks of segmented memory.
| h2odragon wrote:
| imagine the intersection of memory protection and address
| aliasing. We could've had layers and layers of more or less
| useless complexity and years of hardware designed so as to be
| impossible to secure, at its most fundamental levels.
| [deleted]
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