[HN Gopher] Intel AVX10: The Successor to AVX-512
___________________________________________________________________
Intel AVX10: The Successor to AVX-512
Author : gautamcgoel
Score : 56 points
Date : 2023-07-24 20:51 UTC (2 hours ago)
(HTM) web link (www.phoronix.com)
(TXT) w3m dump (www.phoronix.com)
| jauntywundrkind wrote:
| This seemed really cool. I'm used to a lot of new instructions &
| boosts, but Intel adding new conditional load/store is a smart
| interesting coupling that could help increase execution unit
| efficiency in a significant way.
|
| > _As out-of-order CPUs continue to become deeper and wider, the
| cost of mispredictions increasingly dominates performance of such
| workloads. Branch predictor improvements can mitigate this to a
| limited extent only as data-dependent branches are fundamentally
| hard to predict._
|
| > _To address this growing performance issue, we significantly
| expand the conditional instruction set of x86, which was first
| introduced with the Intel(r) Pentium(r) Pro in the form of CMOV
| /SET instructions. These instructions are used quite extensively
| by today's compilers, but they are too limited for broader use of
| if-conversion (a compiler optimization that replaces branches
| with conditional instructions)._
|
| > _Intel(r) APX adds conditional forms of load, store, and
| compare /test instructions, and it also adds an option for the
| compiler to suppress the status flags writes of common
| instructions. _
|
| https://www.intel.com/content/www/us/en/developer/articles/t...
|
| I didn't understand everything about the "caller-saved volatile"
| new general purpose register interface & legacy compatibility.
| But some potentially really interesting optimizations where
| load/store being dual register capable, and being capable of
| staying on the AVX unit & not having to go further out to
| "memory" (caches?):
|
| > _Generally, more register state will need to be managed at
| function boundaries. In order to reduce the associated overhead,
| we are adding PUSH2 /POP2 instructions that transfer two register
| values within a single memory operation. The processor tracks
| these new instructions internally and fast-forwards register data
| between matching PUSH2 and POP2 instructions without going
| through memory._
|
| Neat stuff. Very superficially reminds me of Semantic Streaming
| Registers on the very novel standalone-ish FPU on PULP's RISC-V
| based Occamy many-core chip. In that the unit is acting in a more
| standalone fashion.
| https://www.youtube.com/watch?v=kMhdq7A3d3I#t=10m https://pulp-
| platform.org/docs/BeniniSC11-22.pdf
| crest wrote:
| Hasn't AMD proven multiple times that a double pumped packed-SIMD
| implementation works well enough? Just the permute operations
| need a full width data path to get reasonable latencies. Intel
| already overplayed their hand with AVX-512 when they still had a
| stronger position. Let's hope they fail to hold back the field
| with their misguided attempts to increase their margin no matter
| the cost (even to their own bottom line).
| shmerl wrote:
| Why did it take around 10 years for AMD to implement AVX-512 and
| will they need to wait as long for this too? Doesn't seem to be
| patent related (patents are 20 years and AVX-512 was introduced
| in 2013?).
| dralley wrote:
| Because Intel implementations of AVX-512 were pretty much
| unusable or not worth using until 2019-2020, so nobody was
| writing much AVX-512, so they didn't need to.
|
| AMD practically resurrected AVX-512 by supporting it across
| both desktop and server products, so it's weird to criticize
| them for taking a while when Intel nearly killed the thing via
| segmentation and poor implementation.
| shmerl wrote:
| I'm not criticizing it, just wondering why it took that long
| and if it was due to patents or not.
| meepmorp wrote:
| Don't Intel and AMD have cross licensing agreements for
| instruction set extensions?
| shmerl wrote:
| That's what I thought too. But somehow AVX-512 took a long
| time for AMD.
| colejohnson66 wrote:
| Implementing an instruction set isn't as easy as "we have
| access to IP"
| dathinab wrote:
| Is someone here who understands the nitty bitty details of
| AVX-512/AVX10 and could tell me what is included which current
| latest gen AMD processors do not support?
|
| Because the only thing I can pick out is the 256bit AVX-512 which
| AFIK recent amd processors do support (including 512bit support)
| both on their normal cores and their new compacted code.
|
| But I don't know much about AVX_ so I'm 100% I missed a bunch of
| stuff and/or limitations with current AMD code (besides it being
| double pumped).
| Falvyu wrote:
| Zen 4 lacks AVX512_FP16 (for 16-bits IEEE floating point
| operations), AVX512_VP2INTERSECT and also lack the Advanced
| Matrix eXtension (AMX) set (if you consider that part of
| AVX512).
|
| https://twitter.com/InstLatX64/status/1646471371558461445/
|
| It's worth noting that 16-bits floating point operations are
| still possible on Zen 4, but using Google's BF16.
| Zandikar wrote:
| AVX512 subsets *NOT* supported on AMD Zen4 (Epyc 9000, Ryzen
| 7000):
|
| - AVX512ERAVX512PF (Knights Landing)
|
| - AVX512 4VNNIW, 4FMAPS (Knights Mill)
|
| - VP2INTERSECT (Tiger Lake)
|
| - FP16 (Cooper Lake)
|
| You can see a table here showing cpu's AVX512 support[0], and
| wikicpu also has that data in a list [1], along with more
| detailed info. It's worth noting all data I can find
| specifically talks about AVX512 support in terms of the
| architecture (Zen4), not anything specific product families
| such as ryzen vs epyc implementations. It's possible there
| is/will be some artificial product segmentation going on (like
| what Intel did retroactively with Alder Lake to disable AVX512)
| but I've not seen any mention of it regarding AMD's products. I
| mention this because Intel has kinda been all over the place
| with AVX512 implementation, and there's a big difference
| between Enterprise and Consumer in how they deliver/treat
| AVX512. AMD obviously is a different company with different
| practices, but with only 1 generation to go off of it's hard to
| speculate on a trend, and AVX512 can be an expensive
| implementation. Point being: It's unfortunately complicated AND
| subject to change.
|
| The "big" one here for ML/DL/AI vs Intel's Sapphire Rapids (and
| presumably going forward) is FP16 not being supported on AMD.
| Of course, it's contextual as to whether that's relevant to you
| though.
|
| [0]:
| https://en.wikipedia.org/wiki/AVX-512?oldformat=true#CPUs_wi...
|
| [1]:
| https://en.wikichip.org/wiki/amd/microarchitectures/zen_4#Ne...
|
| My experience is primarily with Intel's implementation of
| AVX512 in their Xeon products for DL/AI. I can expand on that
| if interested, but unfortunately haven't had a chance to play
| with AMD Zen4 yet in that domain, and it's gonna be a while
| till I can get hands on with a Epyc 9000 probably.
|
| EDIT: Fixed typos
| jcranmer wrote:
| > Is someone here who understands the nitty bitty details of
| AVX-512/AVX10 and could tell me what is included which current
| latest gen AMD processors do not support?
|
| Half-precision floating-point for sure.
| zokier wrote:
| Afaik the thing Zen is missing currently is FP16.
| Am4TIfIsER0ppos wrote:
| Slow down dammit! I've barely started writing avx512 since they
| became worth it on ice lake.
|
| > being able to work for both P and E cores
|
| Oh yes I forgot they were gimping their own processors.
|
| > the converged version has a maximum vector length of 256-bits
| [on] the E cores while P cores will have optional 512-bit vector
| use
|
| Maybe they shouldn't have made xmm and ymm "extensions" to the
| base set to begin with.
| eklitzke wrote:
| Extension in this context basically just means new
| registers/instructions that didn't exist on a 386. Even
| floating point support on x86 is technically an extension. SSE
| (which adds the xmm registers) has existed on all x86 CPUs made
| by Intel in the last 20+ years, and the ymm
| registers/instructions are part of AVX2 which has existed on
| all x86 CPUs made by Intel in the last 10+ years.
| phkahler wrote:
| Can we get great RISC-V cores from Apple or AMD please with that
| vector ISA so we can shut down this whole notion of ISA as a
| product differentiator?
| camel-cdr wrote:
| Intel horse creek, sadly won't include the vector isa, just
| RV64GBC.
| dragontamer wrote:
| One of the reasons to use Intel is that their L1 cache is sized
| to 512-bit operations.
|
| AMD Zen4 has 256-bit load/store to L1 cache, which means it'd
| take a load/store unit 2-clock ticks to execute any 512-bit
| load or store. (Though Zen4 has multiple load/store units, so
| maybe its not that big of a deal in practice).
|
| -------------
|
| GPUs are 32-wide with 32-bits each, or 1024-wide operations in
| practice. GCN was 64-wide with 32-bits each or 2048 wide in
| practice.
|
| The reason why AVX512 was a big deal isn't the width btw. But
| instead the design of the instruction set. AVX512 is the most
| advanced CPU vector instruction set ever made, with huge
| inspirations from NVidia's PTX or AMD's GCN.
|
| Of course, GPU-assembly remains superior. I don't think that
| RISC-V (or whoever) should be copying AVX512 or even AVX10,
| they should be looking at NVidia PTX or NVidia SASS as
| inspiration.
| camel-cdr wrote:
| > AVX512 is the most advanced CPU vector instruction set ever
| made, with huge inspirations from NVidia's PTX or AMD's GCN.
|
| Can you explain what makes it the above? I haven't really
| worked with avx512 before, only up to avx2 and rvv.
| codedokode wrote:
| From the name I thought that they extended registers to 1024
| bits, but it looks like instead they made 512-bit width support
| optional.
| canucker2016 wrote:
| from https://cdrdv2.intel.com/v1/dl/getContent/784343 ("The
| Converged Vector ISA: Intel Advanced Vector Extensions 10"
| Technical Paper PDF)
|
| "Intel AVX10 Version 1 will be introduced for early software
| enablement and supports the subset of all the Intel AVX-512
| instruction set available as of future Intel Xeon processors with
| P-cores, codenamed Granite Rapids, that is forward compatible to
| Intel AVX10. This version will not include the new 256-bit vector
| instructions supporting embedded rounding or any of the new
| instructions and will serve as the transition base version from
| Intel AVX-512 to Intel AVX10.
|
| Intel AVX10 Version 2 will include the 256-bit instruction forms
| supporting embedded rounding as well as a suite of new Intel
| AVX10 instructions covering new AI data types and conversions,
| data movement optimizations, and standards support. All new
| instructions will be supported at 128-, 256-, and 512-bit vector
| lengths with limited variances. All Intel AVX10 versions will
| implement the new versioning enumeration scheme."
|
| And who knows when AMD will have time to update Zen ?
| architecture with these new instructions.
| colejohnson66 wrote:
| That's a massive extension. 32 GPRs! And they're finally reusing
| an encoding made reserved in long mode (D5 - AAM in legacy
| modes).
|
| Guess Intel's feeling the pressure from Zen 4 supporting AVX-512.
___________________________________________________________________
(page generated 2023-07-24 23:01 UTC)