[HN Gopher] AMD Introduces World's Largest FPGA-Based Adaptive S...
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AMD Introduces World's Largest FPGA-Based Adaptive SoC for
Emulation
Author : hasheddan
Score : 91 points
Date : 2023-06-27 14:57 UTC (8 hours ago)
(HTM) web link (ir.amd.com)
(TXT) w3m dump (ir.amd.com)
| VoxPelli wrote:
| So, will CoreScore get a new leader? https://corescore.store/
| guepe wrote:
| I'm close to this (I work in emulation) and that chip IS awesome.
| It is the first fpga really designed with emulation in focus.
| Lramseyer wrote:
| Since so many people are asking what "emulation" is, I'm going
| to respond to the parent comment instead:
|
| "Emulation" refers to emulation of chip designs. When a chip
| has billions of transistors that are all connected to each
| other to perform higher level functions, you need to test out
| designs in order to make sure those higher level functions
| actually do what you expect them to. Most modern chip designs
| (at least the digital portions of them) are designed using
| what's called a Hardware Description Language or "HDL" such as
| System Verilog or VHDL. It's somewhat similar to traditional
| programming, except threads are nonexistent, so it's
| essentially an unholy bastardization of a markup language and a
| programming language. But I digress... These functions are then
| synthesized into their low level building blocks such as buses,
| gates, and registers, and are placed and laid out on a chip.
|
| Going back to the part about billions of transistors; as you
| might imagine, testing of such designs must be rigorous and
| thorough. Only problem is that it's really, really
| computationally intensive. There are 2 ways of doing it:
| Simulation (CPU Based) and Emulation (FPGA Based) Simulation is
| slower, but yields more data like waveforms and whatnot (though
| you can get waveforms with emulation, but there are more
| limits.) Also, simulation takes less time to compile, since
| there's no place and route step.
|
| I should also point out that there are 4 key simulation levels:
| Simulation Model (usually compiled C code) RTL Simulation
| (Functional level simulation) Gate level Simulation (simulating
| the individual gates) and physical simulation (where the
| transistors and trace routing are all accounted for.) Each
| level being roughly an order of magnitude more computationally
| intensive than the previous. Most time and engineering effort
| is spent on RTL level simulation, which is what can, and is
| often emulated on an FPGA, and why this product is so relevant
| to hardware designers.
| jonny_eh wrote:
| What does "emulation in focus" mean?
| currio wrote:
| Can you please tell us, who don't work in the field, what makes
| this chip awesome
| Taniwha wrote:
| This chip is for other chip designers - basically when doing
| chip design you want to make a product that works first time
| (or explain to your boss why he should spend hi 6 figures on
| a spin) - so you test test test ... what this is for is that
| a chip team will take their verilog design, compile it into
| luts and load it up here, it will likely run at ~10% of your
| designed speed - the alternative is compiling your verilog to
| code and have it run at 0.1% - 100x more testing
| adwn wrote:
| > _It is the first fpga really designed with emulation in
| focus._
|
| Not really. In each generation of devices, Xilinx had one
| focused on emulation for while now: huge number of LUTs, huge
| number of general purpose IOs, relatively few DSP elements, a
| moderate amount of block RAM. Before this monster, it was the
| Virtex Ultrascale+ VU19P, and before that, the Virtex
| Ultrascale XCVU440, and before that, the Virtex 7 XC7V2000T.
| [deleted]
| shrubble wrote:
| Do they give you the tools/software for free, or do you have to
| buy that separately?
| aseipp wrote:
| Not for these chips. The Vivado licensing is kinda complex
| these days because it's basically segregated by the chip series
| rather than actual software features. But it can basically be
| summed up as "Free for low/mid-range devices with all features,
| free for people using Alveo accelerators and specific
| UltraScale SKUs, and pay us money for anything else."
| monocasa wrote:
| So question: my understanding was th atat one point the cadence
| hardware emulators weren't FPGA based at their core, but instead
| custom chips with a sea of little one bit processors that only
| knew about logic ops (with some FPGAs for interchip routing). Is
| Cadence using FPGAs for logic now too?
| throwaway280382 wrote:
| Yes. Cadence now has two products. One is custom chip based
| emulator. Another is FPGA based. I worked on the first version
| of FPGA based emulator.
| wmf wrote:
| It looks like they have two versions:
|
| "Palladium Z2 emulation based on a new custom emulation
| processor offers fastest, most predictable compiles and most
| comprehensive pre-silicon hardware debug capabilities
|
| Protium X2 prototyping based on latest Xilinx UltraScale+ VU19P
| FPGAs offers highest performance and fastest bring-up times for
| pre-silicon software validation of billion-gate designs"
|
| https://www.cadence.com/en_US/home/company/newsroom/press-re...
| zackmorris wrote:
| Finally! I've waited 25 years for something like this, which
| totally derailed the career I had envisioned for myself. I might
| even lose the option of making fun of all new chips for providing
| marginal performance increases for exponentially growing
| complexity, and have to find a new shtick.
|
| A few predictions/concerns:
|
| * I can't find a price, so I'm predicting that it will be over
| $1,000 which will prevent it from going mainstream (and also be
| ~10 times more expensive than it should be).
|
| * There will be poison pill(s). Maybe flash memory that can only
| be written 1000 times, preventing its use for evolutionary
| hardware and genetic algorithms. Maybe the place-and-route
| software won't be good enough to prevent short circuits, so
| certain configurations will burn up. Maybe some aspect of the
| software will be proprietary and/or encumbered by patents,
| preventing hobbyists from thinking outside the box and "getting
| real work done".
|
| * Any dedicated hardware like memories, ALUs, etc may be
| misaligned for various use-cases. I just want an array of RISC-V,
| Arm, DEC Alpha, PowerPC 601/603, something like that, starting
| with 2 and topping 100 or 1000 cores eventually. So where I'll
| need memories near CPUs, something in the FPGA will lack the
| interconnect to allow that.
|
| I hope I'm wrong about any or all of these. Price I can live
| with, as long as economies of scale or competition kick in and
| eventually deliver something under $1,000. The rest of it.. eh,
| I'm not holding my breath. I've been underwhelmed by all previous
| FPGAs, but maybe they didn't count. Maybe this is something new
| that finally manifests the original vision of what FPGAs could
| be.
| adwn wrote:
| > _I can 't find a price, so I'm predicting that it will be
| over $1,000_
|
| Try 50x to 100x that at quantity=1. This is not a hobbyist
| device: this FPGA is the largest you can get on, and it's
| tailored to the needs of companies that spend 7-9 figures on
| the verification and validation of their ASIC projects.
|
| > _Maybe this is something new that finally manifests the
| original vision of what FPGAs could be._
|
| Even small to mid-sized modern FPGAs have far surpassed the
| "original vision of what FPGAs could be".
| imtringued wrote:
| AMD CPUs see major performance increases every generation. The
| 7700XT is more than 100% faster than the 2700X and that is at
| the same core count. Higher core counts beyond 8 cores have
| become much more accessible.
|
| Having thousands of dumb cores is pointless unless you want to
| work with sparse data. An out of order core isn't bottlenecked
| by compute, it is mostly bottlenecked by memory access latency
| and also bandwidth if you do end up using vector instructions.
| This means most of your core will be memory and your thousand
| core chip will turn back into a dozen core chip. If you need a
| dumb accelerator, then GPUs already exist and you don't need a
| custom chip.
|
| So the only remaining usecase is sparse data. The expectation
| is that you are going to get cache misses all the time anyway,
| so the benefit of a large cache is negated by the fact that the
| same data is rarely accessed again. The problem with this idea
| is that sparse workloads are pretty rare. The only usecase that
| could possibly benefit from a custom chip is sublinear machine
| learning (SLIDE) which basically does nothing but predict which
| neurons are activating and ignore everything else.
|
| Oh also I am already assuming you want to tape out your chip
| and that the FPGA is just a stepping stone. If all you do is
| insist on running softcore processors with no special
| architecture (e.g. the Reduceron) on an FPGA then the whole
| exercise is meaningless.
| LeifCarrotson wrote:
| > _I 've been underwhelmed by all previous FPGAs, but maybe
| they didn't count. Maybe this is something new that finally
| manifests the original vision of what FPGAs could be._
|
| It sounds like you're frustrated with hardware manufacturers
| for a slight against supporting your use case. But I think that
| on closer inspection, you're really frustrated with economics,
| physics, and the nature of the universe.
|
| It's part of the nature of semiconductor manufacturing that
| manufacturing a custom ASIC (or massively-general-purpose IC?)
| especially a large and complex one, is going to be very
| expensive. There are huge non-recurring costs that can get
| amortized over each unit, plus economies of scale that kick in,
| when your masks can be used for production runs of thousands or
| millions of chips. It's not 10x more expensive than it should
| be so they can make 90% profit when you compare it per unit of
| silicon area against the millions of Zen3 chiplets that AMD has
| sold, it's 10x more expensive because it has fixed costs and
| they're only going to sell a few thousand of them.
|
| As a result of that, you want to spend as little as possible to
| make a product that's usable by as many people as possible. If
| a thousand companies can use this FPGA with flash/EEPROM/fuses
| that have relatively low write endurance, but it's more
| expensive and difficult (or eliminates thousands of use cases!)
| to use SRAM with huge write endurance for settings that will
| typically be written once and, on dev units, a few dozen to a
| few hundred times, that's not an intentional poison pill
| sabotaging your career but just reasonable economics and good
| sense. Plus, if you're trying to recover NRE, an obvious avenue
| for recovery of some of those funds that you spend writing the
| software is to make the software proprietary so you can sell
| Vivado licenses to each of those customers.
|
| On a 2-dimensional planar die, you can add a few layers, but
| you can't change the mathematics of graph theory to get 3D or
| 4D or infinite connectivity. Interconnect is just plain
| expensive. It's always going to be an engineering tradeoff
| between power dissipation and speed, so they make a best guess
| as to where the most applications will need interconnect, and
| build that. The fundamental software gates that are used to
| build them are always going to be slower than dedicated
| hardware gates, because it takes additional transistors to run
| a signal through them. That's why memories, ALUs, CPU cores,
| and peripherals on an FPGA SOC are hard-coded into the chip.
| They're hardcoded in ways that allow you to flexibly make use
| of them with custom logic, but they're burned into the die
| because that's better performance for their users.
|
| You can't physically call into being a few cubic nanometers of
| doped silicon to form a new gate when you downlonew bitstream
| to an FPGA - and putting P or N doped silicon in just the right
| spot is critical to designing a chip, so how in the world do
| FPGAs actually work? They cheat, instead of building actual
| logic gates they just move charges to build the same truth-
| table out of generic SRAM-based look-up table, which means
| working at a layer of abstraction several steps ad a up the
| stack. The idealized, oversimplified, conceptual model of an
| FPGA as identical to a mask-programmable integrated circuit,
| except field-programmable, doesn't exist.
| crote wrote:
| For those wondering what an "Adaptive SoC" is supposed to be:
|
| It is essentially an FPGA packed together with some ARM cores and
| interconnects into a single chip.
| gjsman-1000 wrote:
| For context, "emulation" here is not referring to emulation for
| video game systems, but for SoC Designers. It could potentially
| be used for that though if the cost wasn't likely very
| prohibitive like most FPGAs (and frankly, the VP1902 price tag is
| likely to be enormous).
| cogman10 wrote:
| And to be clear, this is a xilinks product. I didn't realize
| they were purchased by AMD, but they are a old FPGA
| manufacturer.
|
| This isn't "FPGA in your CPU" sort of thing but rather just a
| generational improvement on existing products.
| tiffanyg wrote:
| Yup, here's info through Xilinx website (without some of the
| confusion possible in the current comparatively early stages
| after acquisition):
|
| https://www.xilinx.com/products/silicon-
| devices/acap/versal-...
|
| Seems there's still a relative dearth of 3rd party articles,
| but probably will see at least some more fairly quickly (w/
| lifting of embargo etc.).
| iamflimflam1 wrote:
| I did my final year project using a Xilinx FPGA back around
| 1992. We put some image processing algorithms for fingerprint
| processing onto it for adaptive thresholding and line
| thinning. There was a lecturer who was very into hardware
| software co-design but had got quite disillusioned with it as
| general purpose CPUs just kept getting faster and faster.
| kcmastrpc wrote:
| So is this a successor to the DE-10 Nano (the board the
| MiSTERFPGA project is based on)?
|
| (after looking at corescore probably not, as it'd be way too
| expensive. that being said, the DE-10 Nano is getting old, are
| there any potential successors coming)?
| aseipp wrote:
| This thing probably costs more than your car. So, no, it is not
| a successor in any meaningful sense. There are a lot of
| alternatives right now that would be an acceptable choice; it's
| mostly that the DE10-Nano has all the mindshare and the Mister
| community behind it.
|
| But, in better news, it looks like Intel is finally getting off
| their asses and actually expanding their newest Agilex series
| to meet their customers across the spectrum, and finally offer
| new alternatives to their Cyclone series, which is used in the
| Nano.
|
| Sometime later this year they are planning to announce the
| "Agilex 3" line, and that -- or the already announced "Agilex
| 5" -- will likely be what you will see in the successor to the
| DE10-Nano. It will still take work to target this chip and get
| it into a board people can readily buy.
| asguy wrote:
| There are many already available, e.g. ZedBoard, someone just
| has to do the work to target these other boards and their
| peripherals/layout.
| MegaDeKay wrote:
| Nothing is really comparable to the DE-10 Nano's combination
| of capacity, embedded ARM cores, memory, HDMI scaler, and
| (most importantly) price. The ZedBoard fails the last test:
| it is a fair bit more expensive than the Nano.
|
| I am keen on the MiSTex project though. The plan is to come
| up with something that is more flexible than MiSTer to
| support different targets. So for example, you might be able
| to target a simpler core to a simpler device and vice versa.
|
| https://github.com/MiSTeX-devel
|
| https://github.com/enjoy-digital/litex
| jhallenworld wrote:
| How about KV260 or KR260? (250K LEs, Ultrascale+ 16 nm)
|
| https://www.digikey.com/en/products/detail/amd/SK-KV260-G/13...
|
| The price is very good for Ultrascale+.
|
| I think something could made cheaper using an Efinix Titanium
| chip, someone should do it. Their own dev. board is too
| expensive:
|
| https://www.efinixinc.com/products-devkits-titaniumti180m484...
| Foobar8568 wrote:
| DE-10 nano is an Intel (Altera) board based on a Cyclone V, I
| don't think there has been any mindful updates in this price
| range at Intel.
| jhallenworld wrote:
| https://www.theregister.com/2023/06/27/amd_versal_fpga_emula...
|
| 77 mm x 77 mm package (a bit larger than my old Pentium Pro)..
| I'm amazed they have any yield for a chip this large at 7 nm.
|
| 18 M LEs. 6864 DSPs. 6865 balls.
|
| How long does place and route take?
|
| $57K for the smaller VP1802..
|
| https://www.digikey.com/en/products/detail/xilinx-inc/XCVP18...
| GuB-42 wrote:
| I guess they can afford to have defects since a FPGA a big grid
| of a many of the same components.
| pclmulqdq wrote:
| None of these chips have defects. They usually work with
| chiplets to improve yield. You used to be able to buy
| defective devices for a discount when you had a design that
| didn't use those components, but I don't think those were
| general-purpose.
| [deleted]
| stagger87 wrote:
| Thankfully that's not the real price. The real price is a
| fraction of this, and any serious outfit will negotiate
| quantity discounts to a tenth of that price. Assuming Xilinx
| can even get you the part...
| Taniwha wrote:
| this is 4 dies in the one package so real die size is likely
| 1/4 of this
| amirhirsch wrote:
| >How long does place and route take?
|
| If you want to avoid 12 hours builds you have to use
| floorplanning, incremental synthesis/implementation, and
| dynamic function eXchange (swappable components). I've been
| able to incrementally change designs to the scale of ~50K LUTs
| (look up tables, 50K LUTs is a big change) in about 15 minutes
| of synthesis and P&R with the rest of the design locked.
|
| (The chip here is about 400x the size of a single 50K LUT
| change so I imagine you could have a 100 hour builds if not
| using floor-planning and partitioning)
| pclmulqdq wrote:
| The last generation was pushing 12 hours on some of my
| computers. I assume that if you pay for a top-of-the-line
| server, you can get one of these done in 4-6 hours or so.
| miga wrote:
| What about upload time?
|
| Is it possible to upload just a small bugfix to bitstream?
| aseipp wrote:
| Programming time isn't exactly instantaneous or fast on
| these; SRAM cells need to all be programmed to the proper
| value for every LUT (2^k SRAM cells needed for a single
| k-LUT; k = 6 in this case), and that typically is either
| done online (JTAG) or through attached flash which is read
| on startup and/or specific commands.
|
| If you want to upload a small bugfix without it taking 10+
| hours, you need to floorplan your design and use "partial
| reconfiguration" techniques in order to change only part of
| the bitstream at a time. This requires a more advanced
| design flow and a bit more work, but is necessary for
| things like multi-tenancy or lowering turnaround times.
| aseipp wrote:
| UltraScale+ you mean? Well, the real question is P&R time at
| some utilization, right? We were easily doing 14hr P&R times
| on fairly utilized US+ chips like, 5+ years ago. We probably
| could have improved this in a number of ways, though.
|
| I'd honestly think that if you just want to throw money at
| it, those absurdly-overclocked gamer rigs that can hit
| sustained +5GHz boosting on just a few cores would be better
| if you want the fastest P&R times? Cloud servers will
| probably have more RAM and memory bandwidth but you can shove
| 128GB of RAM in the 13900K, memory requirements are
| relatively easy to meet IMO. Synthesis can definitely scale
| with some more cores in Vivado (OOC synth) but P&R never
| seemed to scale beyond what you can just get in a desktop.
| YMMV I guess.
| pclmulqdq wrote:
| Yeah, I meant Virtex UltraScale+ parts. I hear that there
| is a small cottage industry of people overclocking
| Threadripper workstations for FPGA synthesis, because the
| memory bandwidth is actually the primary limiting factor
| (and the Threadrippers have the same kind of turbo
| capability as the gaming rigs). I assume that the "x3D"
| chips help a lot, but I don't know.
| aseipp wrote:
| Yeah, you often see it come up in lots of discussions
| among indies or small teams, since people end up just
| buying One Server that runs all their builds; I didn't
| think about AMD's V-Cache though, the 7950X3D is packing
| 144MB of L3 which would be interesting to test. It would
| also be interesting to see something at sustained high
| turbo speeds with a nice, wide LPDDR5X bus like Apple has
| done, too.
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