[HN Gopher] Skybox: Open-Source Graphic Rendering on Programmabl...
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Skybox: Open-Source Graphic Rendering on Programmable RISC-V GPUs
Author : PaulHoule
Score : 23 points
Date : 2023-04-18 19:51 UTC (3 hours ago)
(HTM) web link (dl.acm.org)
(TXT) w3m dump (dl.acm.org)
| ricksunny wrote:
| Note this Skybox is unrelated to the geospatial imaging company
| that Google acquired in 2014 and then sold to Planet in 2017.
|
| https://spacenews.com/planet-to-acquire-terra-bella-from-goo...
| nine_k wrote:
| Silly question: how can a GPU be RISC-V? Isn't RISC-V a normal
| "scalar" ISA with some moderate vector extensions at best?
| wmf wrote:
| SIMT is interesting because each thread looks like scalar code
| but multiple threads are executed in lockstep using parallel
| pipelines. They only had to add a few instructions (section
| 2.3) to enable RISC-V to support SIMT.
| tiedieconderoga wrote:
| Check out figures 1 & 5.
|
| Best I can tell from skimming, it looks like the command
| processor and the grid of compute cores both probably use a
| RISC-V ISA, and the "shader cores" have some custom extensions.
|
| It looks very cool, I wonder if they published the RTL
| anywhere.
| [deleted]
| Steltek wrote:
| It reminds me of
| https://en.wikipedia.org/wiki/Larrabee_(microarchitecture) -
| Intel wanted to make a GPU out of dozens upon dozens of tiny
| x86 cores. I think the idea was start building an x86 moat
| around CUDA (ha).
| pjmlp wrote:
| Indeed and now AVX is what is left of it.
|
| The idea was good, the execution not so much.
| RobotToaster wrote:
| Reminds me of the transputer
| https://en.wikipedia.org/wiki/Transputer
| kjs3 wrote:
| That was exactly what came to mind as well. "Big" RISC-V
| performance oriented cores for apps, gobs of "small" RISC-V
| cores ganged together for GPU. Larrabee didn't work out so
| good, though.
| PaulHoule wrote:
| Skybox is closer to the old 1970s-1980s SIMD machines like
| ILLIAC and the Connection Machine or (I think) the current
| NVIDIA, it has two sets of added instructions, one has to
| do with managing multiple 'wavefronts' (like threads) that
| run the same instructions with the possibility of turning
| some off (predication, which was deliberately left out of
| RISC-V, would have been a help). The other instruction
| control fixed function units and do fused integer multiply-
| adds. I don't see any talk about vector instructions.
| yellowapple wrote:
| Even CPUs without any vector instructions at all can still do
| operations on vectors; they just have to do them "the hard
| way": slowly. This worst case ain't the end of the world if
| each core is fast enough and you have enough cores.
|
| In this case, the design (AFAICT) uses RISC-V's support for
| extensions to add some GPU-specific instructions for things
| like vector math and texture lookups.
| raphlinus wrote:
| This looks like it has fairly similar goals and implementation
| choices as RV64X. I didn't immediately see them citing that
| previous work, but I've only skimmed it so far. In any case, I
| love seeing work like this.
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