[HN Gopher] Interlaken: The ideal high-speed chip-to-chip interf...
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       Interlaken: The ideal high-speed chip-to-chip interface?
        
       Author : peter_d_sherman
       Score  : 14 points
       Date   : 2023-04-16 19:06 UTC (3 hours ago)
        
 (HTM) web link (www.design-reuse.com)
 (TXT) w3m dump (www.design-reuse.com)
        
       | peter_d_sherman wrote:
       | Related: https://en.wikipedia.org/wiki/Interlaken_(networking)
        
       | TristanBall wrote:
       | How does this compare to something like pcie? Why would someone
       | use on over the other?
        
       | rektide wrote:
       | RiscV & open chips seem to all be sticking to TileLink, an early
       | intra & inter-chip interface. I keep wondering how long it will
       | hold, or whether well see some other interfaces come play.
       | 
       | I forgot about Interlaken. Might be useful, maybe?
        
         | ajb wrote:
         | Tilelink seems to be a memory interface, including cache
         | coherency; Interlaken is a packet interface - each could be
         | built on the other, but with less efficiency.
        
       | phendrenad2 wrote:
       | I prefer good old AXI4
        
         | pclmulqdq wrote:
         | AXI4 is only really used within a chip. This is an inter-chip
         | interconnect. It's also an old one, and I'm not sure it's
         | actually a good solution.
        
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       (page generated 2023-04-16 23:01 UTC)