[HN Gopher] The Rise of the Chiplet
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The Rise of the Chiplet
Author : 11thEarlOfMar
Score : 55 points
Date : 2023-04-05 15:37 UTC (7 hours ago)
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| ChuckNorris89 wrote:
| I'm a bit baffled about chiplets stealing all the headlines in
| the tech news sites ever since AMD started using them in Ryzen,
| with people preaching this to be _the_ AMD & TSMC killer
| innovation when actually we've seen them in consumer chips for
| over 15 years now, from Intel at least
|
| The Intel Pentium D in 2005 was basically two Pentium CPU dies
| glued close to each other on the same package to create the first
| ever consumer dual core CPU.[1]
|
| The Intel Core 2 Quad from 2007 was basically two separate Core 2
| Due dies glued close to each other on the same package to create
| the first ever quad core consumer CPU.
|
| I had a 2011 laptop with an Intel P4600 Celeron chip that had the
| discrete CPU die and GPU dies separated, both on the same
| package.[2] I remember this clearly since I first took it apart
| to clean the fan and apply new thermal paste and I was surprised
| to see two different dies on the package.
|
| And those are the chiplet based chips I know off the top of my
| head, there probably are even more earlier designs I don't know
| about, so is there some hidden chiplet agenda that sprung up
| recently which I'm missing or what's going on?
|
| [1] https://www.hardwarezone.com.sg/m/feature-intels-pentium-
| xe-...
|
| [2] https://www.x86-guide.net/Xhoba/en/collection/Intel-
| Celeron-...
| dragontamer wrote:
| Interposers.
|
| The start of "modern" chiplets was AMD's R9 Nano GPU, which I
| believe was the first to use HBM / stacked memory. Each stack
| has 1024 microbumps, and the GPU has 4 stacks, meaning 4096
| bumps/pins connect the GPU with its RAM. EDIT: The pitch
| between these microbumps is 40 microns / 0.040 milimeters.
|
| This technology is "advanced packaging", the ability to provide
| thousands, or even tens-of-thousands, of bumps / effective pins
| to serve the signals going across our computers.
|
| -------------
|
| Yeah, chiplets or even socket-to-socket communications, have
| existed for decades. But today we can take advantage of
| thousands, tens-of-thousands, or even hundreds-of-thousands of
| external "pins" that connect these components together.
|
| Here's a rundown on Intel's technology:
| https://www.anandtech.com/show/16823/intel-accelerated-offen...
|
| > Intel is also stating today that it will be using its second
| generation Foveros technology on the platform, implementing a
| bump pitch of 36 micron, effectively doubling the connection
| density over the first generation.
|
| 36 microns, or 36 um (micrometers) pitch density on Intel's
| advanced packaging technology. That's a lot of pins per mm^2!
|
| Now I don't know how these guys are lining up 0.036 milimeter
| bumps and reliably making connections. I kind of imagine a very
| tiny soldering iron, but I'm probably wrong.
|
| -------
|
| In practice, AMD has led the way. Not only with "chiplets", but
| also off-die L3 cache (aka: x3d cache), adding 64MB of external
| SRAM to their chips through advanced packaging. So these
| thousands-of-microbumps are fast, reliable, and low-power
| enough to provide full-speed caches (something not quite
| possible with those earlier Pentiums you were talking about).
| natpalmer1776 wrote:
| Marketing & viral awareness go brrrrrr
|
| _Edit since this was pretty low effort and likely violates the
| community guidelines I 'll add this:_
|
| I would guess the reason for seeing more content related to
| chiplets and their implications is due to a combination of
| seeing a big player adopt them for their main product line(s)
| and the resulting PR / marketing buzz that occurs as a result
| of that having 'trickle down' effects on the general industry
| discourse as a whole.
| tdba wrote:
| Also the USG is making a big push to reshore chip
| manufacturing, especially in more future-facing areas such as
| chiplets.
| natpalmer1776 wrote:
| Took me longer than I care to admit to realize that USG
| stood for United States Government.
|
| Regarding the statement, I also would point out that there
| is an almost global push towards promoting domestic chip
| manufacturing and reducing the reliance on globalization of
| critical infrastructure, not just in the United States.
|
| In my geopolitical armchair expert opinion, I would guess
| this is in part caused by the conflict in Ukraine as well
| as rising tensions between the various 'global powers'
| further compounding the general loss of confidence that
| followed COVID-19.
| tdba wrote:
| This push began before Covid and well before the war in
| Ukraine went hot - but those two factors certainly
| increased the urgency. At root the push in the US began
| due to the rise of China as a military competitor in the
| early 2010s, and the consequent realization that TSMC
| might be blockaded, captured or destroyed.
| cma wrote:
| Pentium D was a multi chip module, and so are AMD's chiplets,
| but Pentium D didn't use chiplets:
|
| > ICs that can perform most, if not all of the functions of a
| component of a computer, such as the CPU. Examples of this
| include implementations of IBM's POWER5 and Intel's Core 2
| Quad. Multiple copies of the same IC are used to build the
| final product. In the case of POWER5, multiple POWER5
| processors and their associated off-die L3 cache are used to
| build the final package. With the Core 2 Quad, effectively two
| Core 2 Duo dies were packaged together.
|
| > ICs that perform only some of the functions, or "Intellectual
| Property Blocks" ("IP Blocks"), of a component in a computer.
| These are known as chiplets.[3][4] An example of this are the
| processing ICs and I/O IC of AMD's Zen 2-based processors.
|
| https://www.wikipedia.org/wiki/Multi-chip_module
|
| It seems chiplets are a different subset but it is very
| similar.
|
| Also, AMD used different process nodes for different parts,
| where that wouldn't make sense in just a dual cpu package, and
| certain circuitry is now starting to scale different as process
| nodes shrink, so they may want a different older process node
| for cache than for logic, etc. which could emphasize the
| different functions aspect and explain why it is in the news
| more. 3d v-cache uses an older node for that reason, though
| needs more thorough connectivity than chiplet tech so uses
| interposers I think.
|
| You might also want to buy third-party IP that is only
| available created with design rules from a different foundry.
| Chiplets let you integrate it, where an approach like SoCs
| wouldn't.
|
| Shot noise is a bigger problem in EUV, so you can potentially
| get better yields by splitting functional components into
| different chiplets rather than the alternative of fusing off
| parts of a chip and selling it as a lower tier. Those are the
| reasons I see as to why they are getting lots of press and
| attention even though the packaging technology may be old.
|
| Initial reasons for mixing nodes may have been more business
| related than technical: AMD had to buy a certain amount of
| output from global foundries after spinning it off.
| stacktrust wrote:
| Open Chiplet Ecosystem Open-Source EDA Toolchain (24h dev
| cycle) RISC-V: open-source / licensed / classified
| Upcoming FPGAs made-in-USA by TSMC Arizona Domain-specific
| accelerators
|
| This interoperability vision aims to improve US chip supply chain
| resilience, integrity, reshoring and reusability of IP blocks in
| the wake of Moore's Law.
|
| _> For chiplet adoption, the industry needs to worry not just
| about the die-to-die interfaces and packaging technology but the
| whole chiplet economy. For example, how to describe a chiplet
| before building it in order to achieve efficient modularity ..
| Some of the other areas to get addressed include: How to address
| known-good-die (KGD) in business contracts. How to accomplish
| architecture exploration? How to handle business logistics?_
|
| Until now, proprietary packaging has limited the "chiplet
| economy". The current iteration of standards initiatives started
| around 2018.
|
| https://www.opencompute.org/blog/the-ocp-open-domain-specifi...
|
| _> Decades of progress with general-purpose CPUs have slowed,
| while performance requirements of workloads have catapulted,
| driving significant demand in domain-specific accelerators ...
| The ODSA subproject's mission is to define an open interface and
| architecture that enables the mixing and matching of silicon
| chiplets from different vendors via an open marketplace onto a
| single SoC._
|
| Linux Foundation, https://www.chipsalliance.org/
|
| _> CHIPS Alliance develops high-quality, open source hardware
| designs relevant to silicon devices and FPGAs ... Companies and
| individuals can work together to develop open source CPUs,
| various peripherals, and complex IP blocks._
|
| In parallel, there is funded university research to create a
| reliable open-source EDA toolchain, https://woset-
| workshop.github.io/WOSET2022.html
|
| _> Chisel and Verilator provide an open-source stack for digital
| design. For ASIC synthesis, we have open-source tools like
| OpenROAD, Yosys, and Magic. OpenROAD is a project to deliver an
| end-to-end silicon compiler in open source. The aim is to
| "democratize hardware design" by providing an automated layout
| generation flow from a design in RTL to GDS files used to produce
| silicon. Google and Efabless offer free production of chips in a
| multi-project wafer if the project is available in open source._
|
| David Patterson & John Hennessy's 2018 Turing Award lecture
| explained why "democratizing hardware design" is needed to reduce
| cost/time for domain-specific computing,
| https://news.ycombinator.com/item?id=18118957
|
| Videos from 2021 DARPA ERI (Electronics Resurgence Initiative)
| conference:
| https://youtube.com/playlist?list=PL6wMum5UsYvaKtr1GOr-rqhD_... &
| https://eri-summit.darpa.mil/2021-Agenda
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