[HN Gopher] Tiny Tapeout: From idea to chip design in minutes!
___________________________________________________________________
Tiny Tapeout: From idea to chip design in minutes!
Author : rbanffy
Score : 63 points
Date : 2023-03-30 17:56 UTC (5 hours ago)
(HTM) web link (tinytapeout.com)
(TXT) w3m dump (tinytapeout.com)
| fsckboy wrote:
| TL;DR (i didn't do a deep dive, just a skim) they've laid out a
| chip into a grid of small areas and you can submit a design for
| one of the areas. Then they make a chip that has everybody's
| designs on them, so when you get your chip it has your design,
| and everybody else's that you can play with. The areas each have
| room for about 400 gates in which people have built stuff like a
| 4 bit CPU. An area in one corner is the "master scheduler", it
| multiplexes and delivers 8 bit input sequentially to each area,
| and gathers 8 bit outputs from each area, at the rate of about
| 15khz.
|
| using all their tools and documentation to create your design is
| free, at a certain point when it gets to committing they have a
| pricing scheme which is intended to be affordable.
|
| (note: they've been doing versions of this, the last one was tape
| out 2, now is tape out 3, and I was not careful about checking
| which version specs I was skimming so perhaps the new one is more
| capacious or the last one less.)
|
| from https://hackaday.com/2023/02/14/supercon-2022-matt-venns-
| tin...
|
| personally, I think it would be just a bit cooler to have a dual
| channel 40kHz system that could do DSP on high quality audio, but
| you can do plenty with this
| Taniwha wrote:
| I submitted 2 CPUs to TT2 and a PDP8 (12 bits) to the current
| TT3.
|
| The major limitations are the relatively small number of gates,
| and the external interface (8 inputs including clock/reset, and
| 8 outputs) - and the external multiplexor which essentially
| limits clock frequencies to tens of kilohertz.
|
| TT4 and later will have a redesigned pin interface and likely
| have roughly twice as many external pins and far faster clocks
| - a lot of my designs are gates spent talking over that tiny
| interface
| Taniwha wrote:
| I'll also note that all Tiny Tapeout projects are hosted on
| github and you can browse through them if you want to see how
| they're done
| actionfromafar wrote:
| I was excited until I saw how you interface with your "corner".
|
| It's so slow. It's a shame, I wonder if there could be some
| other way?
| fsckboy wrote:
| actually, combining what i said with what you said got me to
| a new idea: if the different areas on the chip were sharing
| inputs and possibly outputs, even with the same bandwidth
| tech, it would be much higher bandwidth as a group.
|
| So, for example, have a whole tape-out project devoted to
| something like a modular music-sampler/synthesizer. So,
| there's D/A A/D of a few audio streams coming in, which every
| area of the chip gets as a feed, but also areas can talk to
| their neighbors directly without multiplexing, and then
| mixers, filters and group output. Maybe some way to "roll
| your own multiplexer" so somebody could use the whole chip
| for a variety of guitar pedals, somebody else a vocal
| processor, etc.
| realworldperson wrote:
| [dead]
| f_devd wrote:
| I wish it was possible to do this without the crowd sourcing, I
| have a low-volume HDL project of just ~40 gates and 32 shift
| registers (+4*32 gates) which discrete is quite bulky, FPGAs are
| overkill and CPLD works but are often too small or unavailable.
|
| Based on rumors maybe atomicsemi will provide this at some point.
| tesseract wrote:
| The smallest Lattice iCE40 are under $2 in volume, it may be
| "overkill" but also pretty tough to beat economically at low
| quantities. Especially keeping in mind one of the limitations
| of these MPW silicon runs is the parts you get are untested...
| reasonable in prototyping but an obstacle to scaling up to low
| volume production.
|
| Dialog (nee Silego) Greenpak is a cheaper programmable option
| if you can find one that your design fits in. The design flow
| is a little more idiosyncratic.
|
| Of course often the cheapest option these days for low-end
| digital logic requirements is to emulate your logic in a
| microcontroller, if you can get away with that speed wise. It
| might not feel very elegant but the economy of scale is tough
| to beat.
|
| Personally it's analog and mixed signal design that I'd love to
| see cheap and easy custom silicon for... I've got a design with
| some DACs, analog switches, jellybean op amps, and a dozen-ish
| discrete transistors that would be really great to integrate
| and miniaturize, but it doesn't seem practical at ~10k volumes.
| jmole wrote:
| The transistors are the hard part to integrate here. From the
| manufacturing side, why waste the die space on your MCU
| production line when you can use a much older process to
| build transistors for pennies.
|
| For mixed signal design in general, the Cypress PSoC 4 series
| is pretty good.
|
| Renesas is also doing a lot of work in the low BOM cost
| configurable analog/digital space, with Greenpak and
| ForgeFPGA:
| https://www.renesas.com/tw/en/products/programmable-mixed-
| si... https://www.renesas.com/tw/en/products/programmable-
| mixed-si...
___________________________________________________________________
(page generated 2023-03-30 23:01 UTC)