[HN Gopher] CPU of the Day: UTMC UT69R000: The RISC with a Trick...
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       CPU of the Day: UTMC UT69R000: The RISC with a Trick (2019)
        
       Author : zdw
       Score  : 43 points
       Date   : 2023-02-26 16:30 UTC (1 days ago)
        
 (HTM) web link (www.cpushack.com)
 (TXT) w3m dump (www.cpushack.com)
        
       | drivers99 wrote:
       | > The UT69R000 [has] a 64K data space and a 1M address space.
       | 
       | So the virtual address space is 1M but it can only physically
       | interface with 64K of memory?
        
         | hummus_bae wrote:
         | The chip itself can have up to 64k Flash (and another 64k of
         | RAM). But the CPU accesses the memory via a MMU that can map
         | the 1M address space into (mostly) 64k chunks. So effectively
         | the OS can use 1M physical addresses and the CPU itself uses
         | close to 64k of them (depending on how you configure the MMU).
         | 
         | edit: so the whole address space of 1M can be mapped via the
         | MMU into 64k installments.
        
       | snvzz wrote:
       | Reminder that RISC/CISC are labels placed upon an ISA (the
       | software-hardware interface).
       | 
       | The microarchitecture (how the CPU is internally designed, how it
       | executes instructions) is irrelevant to RISC vs CISC.
        
         | steponlego wrote:
         | This might be mostly true now but wasn't always.
        
       | somat wrote:
       | If curious as to what a 1750 architecture cpu is. there is this.
       | 
       | http://www.xgc-tek.com/manuals/mil-std-1750a/
        
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       (page generated 2023-02-27 23:01 UTC)