[HN Gopher] Designing My Own ASIC with Tiny Tapeout
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       Designing My Own ASIC with Tiny Tapeout
        
       Author : picture
       Score  : 29 points
       Date   : 2023-01-25 20:33 UTC (2 hours ago)
        
 (HTM) web link (teaandtechtime.com)
 (TXT) w3m dump (teaandtechtime.com)
        
       | MayeulC wrote:
       | Awesome! Can one submit semi-custom or full-custom layouts as
       | well as digital logic?
       | 
       | We have FPGAs for (most) logic stuff, but what if I wanted a
       | tiny, power-efficient RF (Wi-Fi or GPS for instance) chip?
        
         | LeifCarrotson wrote:
         | Can you do it in 1000 logic gates, in a size of 150 x 170 um?
         | 
         | There are very few things that are more complex than toys which
         | fit in that space. It's primarily a learning opportunity, not a
         | hack to build a product.
         | 
         | Also, most of the hard work in Wi-Fi and GPS modules is not in
         | receiving the binary radio signal but in the protocols to
         | decode it. For wifi, the 802.11 protocol would require your PHY
         | to provide at the very least the orthogonal frequency-division
         | multiplexing, but you're probably expecting something closer to
         | a Wiznet chip that provides the fundamental stack available
         | from eg. the lwIP project.
        
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       (page generated 2023-01-25 23:00 UTC)