[HN Gopher] RISC-V SBC VisionFive 2 Officially Shipped
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       RISC-V SBC VisionFive 2 Officially Shipped
        
       Author : britneybitch
       Score  : 103 points
       Date   : 2023-01-11 15:48 UTC (7 hours ago)
        
 (HTM) web link (www.starfivetech.com)
 (TXT) w3m dump (www.starfivetech.com)
        
       | sacnoradhq wrote:
       | ~ 10% $ of Xilinx demo boards.
       | 
       | Curious: Is there a "Ferrari" general RISC-V ISA shorthand or CPU
       | implementation with more extensions including Q B V K H & S ?
        
       | _joel wrote:
       | Explaining Computers "StarFive VisionFive 2 RISC-V SBC review,
       | including a demo of an engineering release of Debian, and of
       | Python GPIO control"
       | 
       | https://www.youtube.com/watch?v=ykKnc86UtXg
        
         | geerlingguy wrote:
         | It's sad how 'being able to actually use GPIO pins in software'
         | is an achievement for an SBC. But I do applaud StarFive for
         | actually seeming to throw some support behind their boards.
         | 
         | We have been spoiled with Raspberry Pi the past few years prior
         | to the shortages. I wish another vendor could get close to Pi's
         | position to give more competition in terms of support and
         | documentation.
        
           | mikerg87 wrote:
           | We should remind ourselves that Raspberry Pis are in
           | abundance, just not in the hobbyist channel. Current
           | situation is not unlike the graphics card shortage when
           | crypto miners were on garaunteed purchase contracts
           | 
           | This board has so much going for it. The native M.2 is a
           | highly desireable feature. The only knock is the lack of
           | wifi/bluetooth which can at least be solved with a dongle.
        
             | somethingwitty1 wrote:
             | The no-wifi seems to just be the kickstarter. When I
             | ordered mine a little while back, they had an option for
             | wifi (extra $8-$10, as I recall). I haven't received it
             | yet...so not sure if it actually does.
        
           | phkahler wrote:
           | >> it's sad how 'being able to actually use GPIO pins in
           | software' is an achievement for an SBC
           | 
           | Yeah, but with an OS and MMU you don't get to just write to a
           | port or other registers. The plumbing has to be in place.
        
       | synergy20 wrote:
       | I have a sifive "unmatched" board sitting here collecting dust,
       | cost me $700 then.
       | 
       | Most projects turned out ARM based after I bought it.
       | 
       | The site is not working, any price of this board? What's its
       | market, e.g. ip camera? I'm still interested in lower cost ready
       | to go risc-v boards.
        
         | gurjeet wrote:
         | I'm looking to buy these boards; recently I bought one on eBay.
         | I plan on using them to add to FOSS projects' buildfarms. The
         | first one I got from eBay is now running Postgres buildfarm.
         | 
         | Please let me know if you're interested in selling me yours.
        
         | m00x wrote:
         | Any reason why it's collecting dust? I have a few RISC-V boards
         | and I haven't had any issues with them other than having to
         | compile almost everything from source.
        
         | rwmj wrote:
         | The Unmatched board is great, a real workhorse for building
         | Fedora packages. It was very expensive at release (as was
         | Unleashed) because of the small run, so we hope the VF2 with
         | better performance far lower price will drive more adoption.
        
         | dkjaudyeqooe wrote:
         | $55/$65/$85 for 2GB, 4GB, 8GB plus shipping
        
       | rahen wrote:
       | How well are Linux and the BSDs supported?
        
         | sacnoradhq wrote:
         | Not this board, but a $$ RISC-V from Xilinx's PolarFire does:
         | 
         | - Yocto Linux BSP
         | 
         | - Buildroot Linux BSP
         | 
         | - Embedded Linux from Siemens Embedded
         | 
         | - FreeBSD (coming soon)
         | 
         | https://www.microchip.com/en-us/products/fpgas-and-plds/syst...
        
       | MisterTea wrote:
       | Where is the CPU hardware manual that tells me the CPU's memory
       | map and registers?
       | 
       | This is why so much hardware ends up in landfills. No thanks to
       | undocumented junk.
        
         | swetland wrote:
         | The _CPU_ itself (Core Complex, including cache, irq
         | controller, etc) is documented by SiFive:
         | 
         | https://www.sifive.com/cores/u74-mc
         | 
         | Unfortunately there appears to be no detailed documentation at
         | all (unless you count a pile of Linux and bootloader patches,
         | which I don't) for the peripherals, etc, outside of the core
         | complex on the SoC:
         | 
         | https://doc-en.rvspace.org/Doc_Center/jh7110.html
        
       | PaulHoule wrote:
       | I am waiting to get mine.
        
       | jacooper wrote:
       | Good luck using it with docker, many images don't support ARM,
       | let alone RISC-V
        
       | sargun wrote:
       | Does anyone know if this SBC contains RISC-V Worldguard
       | capabilities (https://www.sifive.com/technology/shield-soc-
       | security)? I've been looking for a RISC-V SBC with a way to
       | protect asymmetric keys. The new ESP32 has a dedicated key
       | storage.
       | 
       | The SoC docs indicate: * 512 x 32-bit (2 KB) of OTP for key data
       | on-die storage
       | 
       | But, that sounds like it's for the likes of secureboot.
        
         | aseipp wrote:
         | No, and there aren't any (public) cores deployed with
         | Worldguard support that I'm aware of, at least none with user-
         | controllable software, nor am I aware of any alternative
         | implementations to Worldguard e.g. FPGA designs for
         | prototyping. Seems like a fairly involved product.
         | 
         | If you just want some kind of trusted key storage/signing
         | inside a secure enclave style design, to keep things secure
         | from the OS/hypervisor, something like Keystone may be more
         | your speed. It largely just re-uses the existing M-mode
         | privilege level to enforce separation from the OS and userspace
         | stack. It isn't 1-to-1 with Worldguard, but it's a start, and
         | in theory you can "just" patch the SBI implementation to
         | support it: http://docs.keystone-enclave.org/en/latest/Getting-
         | Started/H...
         | 
         | Anything implemented today is probably going to be missing some
         | key features of a complete stack, but the parts are all mostly
         | there, and still moving.
        
       | psychphysic wrote:
       | I received mine weeks ago.
       | 
       | There are several desktop images but various issues reported from
       | no display output, to only 1080p supported. To this image or that
       | one working.
       | 
       | Important note, the later images require an updated to uboot and
       | SPL, either with the bootrom or a serial connection.
       | 
       | It's a mess at the moment!
        
         | andrekandre wrote:
         | > It's a mess at the moment!
         | 
         | yea, thats for sure, but i think a lot of promise too...
         | 
         | from my cursory testing it seems gui performance is much better
         | than hifive unmatched (window manager, apps, web browser)
         | 
         | [edit] add geekbench
         | 
         | https://browser.geekbench.com/v5/cpu/compare/17159543?baseli...
        
           | fathyb wrote:
           | > 1 Processor, 1 Core, 4 Threads
           | 
           | Any idea why StarFive went with this choice for an SBC? I
           | remember POWER7 also having 4 SMT, but it felt right for a
           | superscalar multi-core CPU.
        
             | photonbeam wrote:
             | It has 4 cores with 1 thread each, rather than 1 core with
             | 4 thread
        
             | rwmj wrote:
             | The link in the GP comment is wrong - both SoCs have 4
             | cores, each with a single thread.
             | 
             | The reason why this SoC is faster than HiFive Unmatched
             | seems to be down to architectural improvements.
        
               | fathyb wrote:
               | Ah, makes much more sense. Thanks!
        
         | smoldesu wrote:
         | Hah, reminds me of my disappointment with the original Pi.
         | Here's hoping they sort it out as fast as they did for ARM!
        
         | NoNameHaveI wrote:
         | Likewise. I believe mine arrived about the 29th. Haven't broke
         | the shrink wrap yet.
        
         | Klasiaster wrote:
         | Does is have UEFI boot support? I guess through u-boot?
        
       | bullen wrote:
       | HN is tanking the RVSpace forum too.
       | 
       | Just go here and buy one instead:
       | https://www.waveshare.com/visionfive2.htm?sku=23875
        
       | sylware wrote:
       | [flagged]
        
       | kfihihc wrote:
       | SDK:https://github.com/starfive-tech/VisionFive2
       | 
       | Docs: https://doc-en.rvspace.org/Doc_Center/visionfive_2.html
        
         | progbits wrote:
         | Looks pretty good opensource-wise, right? Some linux fork with
         | ton of patches but hopefully most of that will get upstreamed,
         | and except that I found no weird blobs or proprietary crap.
        
           | simcop2387 wrote:
           | I haven't looked at the v2 but they seemed to be doing an
           | alright job at getting things upstreamed with the v1. the
           | only thing i remember seeing that wasn't very good in that
           | regard was the neural net stuff that they had and that seemed
           | more from just issues getting the hardware working than any
           | nda or lack of desire to do it. I'd hope that the v2 is
           | similarly worked through even if it needs some non-upstream
           | patches at the start just because it's new hardware and it
           | takes time.
        
             | geerlingguy wrote:
             | It seems like many SoCs (also in ARM space) advertise '2
             | TOPS' or however many TOPS neural processors integrated in
             | the silicon... but the actual number of SoCs where those
             | coprocessors can be used in Linux seems to be very low.
        
           | kfihihc wrote:
           | I think it will push to upstream ASAP.
        
           | swetland wrote:
           | Still no sign of an actual Technical Reference Manual or any
           | other detailed documentation on the SoC (registers,
           | peripherals, etc). A big pile of Linux patches, while better
           | than nothing, is a poor substitute for actual documentation.
           | 
           | SiFive does provide docs for the core complex (processors,
           | cache, irq controller, etc), but that doesn't cover any SoC-
           | specific peripherals.
        
             | progbits wrote:
             | Agreed. But I feel like that is still a step ahead of RPi
             | where you get random firmware blobs for the GPU without
             | which it won't even boot.
        
               | swetland wrote:
               | It's definitely nicer to have source than a bunch of
               | opaque binaries. (Is there source for the full boot path?
               | Sounds like they have patches for OpenSBI and u-boot --
               | didn't see if there was source or docs for the on-die
               | boot rom.)
               | 
               | I just find the "all you need is Linux patches" approach
               | annoying. There are BSD variants and little experimental
               | and homebrew OSes out there that would be fun to run on a
               | capable RISC-V SBC and even if you are using Linux it's
               | still nice to have some documentation to refer to beyond
               | whatever the silicon vendor implemented in various driver
               | patches.
        
       | davidlt wrote:
       | Upstreasming status: https://rvspace.org/en/new-
       | page/JH7110_Upstream_Plan
       | 
       | StarFive Tech. have been upstreaming on kernel, OpenSBI and
       | U-Boot from several weeks now. Of course this is still
       | weeks/months away (if not more, for all the features) from
       | landing in stable releases. Even more for distributions to pick
       | those up.
        
         | Klasiaster wrote:
         | https://web.archive.org/web/20230111211739/https://rvspace.o...
        
       | UltraViolence wrote:
       | Don't buy from this company. They can't even keep their website
       | up from the strain of a few HN readers.
        
       | bhouston wrote:
       | Any performance comparisons with Raspberry Pi boards? How does
       | this RISC-V CPU stack up against them?
        
         | pmw wrote:
         | Not great; VisionFive appears to be significantly less
         | performant.
         | 
         | https://browser.geekbench.com/v5/cpu/compare/17159543?baseli...
        
           | CUViper wrote:
           | There are a few where it does win though -- I wonder what
           | characteristics favor VisionFive in those?
        
           | viraptor wrote:
           | We're still in the early days of risc-v availability. Arm has
           | been widely deployed and the compilers optimised by both
           | individuals and companies. I expect this comparison to look
           | better in a year (not better than rpi4, just a smaller gap)
        
           | andrekandre wrote:
           | afaict rbpi cpu has vector instructions?
           | 
           | if so, i wonder how much that contributes to the
           | difference...?
        
             | adgjlsfhk1 wrote:
             | a lot.
        
         | rjsw wrote:
         | A board that you can buy will perform better than one that is
         | unavailable.
        
           | chris_overseas wrote:
           | For what it's worth, I managed to get an RPi4 at retail price
           | within a few days by setting the appropriate filters on
           | https://rpilocator.com and keeping a watch on it with an
           | Android app called "Web Alert". I've used the same trick to
           | buy out-of-stock cameras and laptops too, works a treat.
        
         | _joel wrote:
         | Faster than a 3 but slower than a 4 by raw clock speed but ymmv
         | with real world usage
        
         | bullen wrote:
         | CPU slower than 4 as said, but even Jetson Nano is slower that
         | the mad performance per watt of the 4.
         | 
         | BUT the GPU is apparently better which would make this THE SBC.
         | 
         | I will test my 3D MMO engine and give exactly what is what once
         | I receive mine, should be a couple of days.
         | 
         | The Raspberry GPU has a serious cache problem, it can't render
         | a triangle at 60FPS in 1080p!!!
         | 
         | But 100 non-instanced animated characters (each with a unique
         | weapon in hand) at 60FPS and low res (800x600).
         | 
         | Jetson (1/2 Nintendo Switch GPU) does 300 at 60 FPS in 1080p.
         | 
         | If the Visionfive 2 is either:                 - 100+ at 60 FPS
         | and 1080p       - 200+ at 60 FPS and 800x600
         | 
         | I'm going ALL IN on Risc-V (my own VM for scripting the engine)
         | and StarFive (buy a few to use as demo for the MMO instead of
         | Raspberry 4/Jetson Nano).
        
           | snvzz wrote:
           | >the mad performance per watt of the 4.
           | 
           | More like bad than mad.
           | 
           | This SoC is far more efficient, using just 4.4w on full load
           | and achieving some 80% of rpi4's cpu performance at a much
           | lower power, with no need for a heatsink.
        
             | bullen wrote:
             | We'll see, if you need a heatsink for this here is one I
             | bought which should fit:
             | http://www.enzotech.com/cnb_s1l.htm
             | 
             | Not going to debate the gflops/w yet, but Raspberry 4 cores
             | are also around 1W each and they kick ass compared to even
             | M1 (much worse OFC, but per $/openess they still win imo)
        
               | snvzz wrote:
               | If the SoC in rpi4 was any good, it wouldn't need a huge
               | heatsink to not throttle.
               | 
               | The reality is that it draws around 10w more often than
               | not.
        
               | bullen wrote:
               | I know what 10W feels like because the Jetson Nano draws
               | that, and Raspberry 4 is 7W with GPU+4 cores saturated.
               | 
               | You will need a heatsink on the Visionfive if the GPU
               | does what I hope it does.
               | 
               | The Raspberry 4 GPU is only 1W vs. 5W on the Jetson Nano!
               | 
               | I'm hoping for a 2-3W GPU on the Visionfive and then
               | you'll need a heatsink for MMO gameplay no question about
               | it.
               | 
               | Longevity is now crucial as hardware peaks, heat kills
               | electronics slowly but oh so surely!
               | 
               | Edit: Do you have a URL for those 3.xW and 4.4W claims...
               | Then I think we wont see 100+ but cache can still be
               | larger so you can have 100 at 1080p and that is enough
               | for mainsteam adoption and replacing all other computers
               | (Switch, PS4, XBOX, phones and pads etc.)!
               | 
               | The future belong to those that compile!
        
               | snvzz wrote:
               | 4.4 W is the figure given for the SoC on full load.
               | 
               | They also give a lower figure that's 3.x W for full load
               | with the GPU off.
               | 
               | It won't need a heatsink, because with its power draw it
               | won't get above 70C even on full load, while the chip is
               | built for industrial temperature range in operation.
        
               | bullen wrote:
               | Do you have a URL for those 3.xW and 4.4W claims?
               | 
               | For longevity 60C is better. I'm talking multiple decades
               | at constant permanent full blast here.
        
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