[HN Gopher] TSMC starts volume production of 3nm chips
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TSMC starts volume production of 3nm chips
Author : rntn
Score : 136 points
Date : 2022-12-29 17:06 UTC (5 hours ago)
(HTM) web link (focustaiwan.tw)
(TXT) w3m dump (focustaiwan.tw)
| imiric wrote:
| A few questions for those familiar with chip production:
|
| 1. How much smaller can we make the silicon process before we run
| into physical limitations? How many years do you think that gives
| us?
|
| 2. What are the most promising alternatives to silicon? Carbon
| nanotubes, photons? How many years are we realistically away from
| these being commercially viable?
| MangoCoffee wrote:
| >What are the most promising alternatives to silicon?
|
| 3d stacking and chiplet
| dotnet00 wrote:
| I think we're getting pretty close to Silicon's limits,
| optimistically maybe 2-3 more node shrinks. After that, I think
| Gallium Arsenide is the next most accessible material which
| should have room for a few more nodes.
|
| By then hopefully those more exotic technologies like carbon
| nanotube transistors will be a bit more viable.
|
| I'm not much of an expert though, just recalling what was
| covered in one of my lectures.
| NovaVeles wrote:
| I am not so keen on photon transistors, at least not in the
| short term. I have seen them proposed for decades but
| progress has been slow at best. Maybe some folks will figure
| it out and we will make that leap but current progress is not
| looking great. As for Carbon nano tubes, I'm not too familiar
| with the applications of this for transistors but it does
| sound like something that can get us a little further down
| the road.
|
| All this arm chair speculation. All the people that work on
| these things would know far better than me. And I mean ALL
| the people! ;)
| yazaddaruvala wrote:
| > 3nm technology would feature an estimated 60 percent gain in
| density of logic transistors and reduce power consumption by 30
| percent to 35 percent at the same rate compared with 5nm
| technology
|
| I'm really looking forward to the new Gravitons and the M3
| Pro/Max/Ultra MacBooks! and what they will be able to achieve.
| picture wrote:
| Smaller transistors does indeed reduce dynamic power
| consumption as transistors can switch with less charge, however
| the leakage current (static power consumption) will rise, more
| than the already significant amounts. I'm not sure how much
| actual energy savings will come from this in an application
| like laptops.
|
| Also, increased density isn't a huge deal as, while it reduces
| the die size which reduces the cost, it also likely costs more
| than an already mature process. It can help with increasing the
| amount of logic gates in series before needing to be pipelined
| to the next clock cycle, but that's not that big of a deal
| either
| Symmetry wrote:
| Leakage power will rise all else being equal, but there are
| plenty of things designers can do to counteract that for
| reasonable costs.
| baybal2 wrote:
| [dead]
| amelius wrote:
| And Apple will take all the credit for TSMC's achievements, as
| usual.
| discordance wrote:
| And ASML will remain in the shadows
| congoe wrote:
| So will Zeiss
| r00fus wrote:
| You do realize that TSMC is heavily bankrolled by Apple
| right?
| keepquestioning wrote:
| Who has the details of this strategic relationship?
|
| Remember Apple's infamous $200 billion cash-pile during the
| peak iPhone era of 2010-2016? How much of it went to TSMC?
| 2OEH8eoCRo0 wrote:
| > what they will be able to achieve.
|
| Who? TSMC and Arm?
| everyone wrote:
| Do they make any 5nm chips other than apple silicon ones? What
| about the 3nm ones, will they all be apple? I would like to put
| one of those new chips in a normal pc.
| mdasen wrote:
| Yes, they make a lot of 5nm and 4nm parts for Qualcomm and
| others. For example, the Snapdragon 8+ Gen 1 is based on TSMC's
| 4nm (the regular 8 Gen 1 is based on Samsung's 4nm). AMD's
| Ryzen 7000 series (Zen 4) uses TSMC's 5nm.
|
| Apple tends to have the best margins and is willing to pay
| upfront for TSMC's capacity so they generally get it ahead of
| other customers. However, there are reports that Intel will be
| using TSMC's 3nm: https://www.windowscentral.com/intel-apple-
| tsmc-3nm-report. Intel has confirmed that it will be using
| TSMC's 3nm tech in its 2023 products, but hasn't said which
| products. Maybe we'll see Intel laptop chips at 3nm, maybe
| it'll be high-margin datacenter chips, maybe it'll be something
| for enthusiasts on the desktop, maybe it'll just be the GPU for
| chips made with Intel 4 (5nm):
| https://www.extremetech.com/computing/338679-intel-may-
| drop-....
| beautifulfreak wrote:
| Intel canceled its order with TSMC.
| https://www.electronicsweekly.com/news/business/intel-
| cancel...
| mdasen wrote:
| Awesome! Great to know
|
| Of course, the article goes on to say that TSMC is reducing
| N3 capacity with Apple being the only customer in 2023.
|
| I think it's just hard to get customers who want to pay
| what Apple is willing to pay.
| shmerl wrote:
| Do AMD plan a 3nm refresh or they'll do it only for next
| generations of chips?
| Grazester wrote:
| Something tells me by the time this trickles down to AMD they
| will be on their next CPU iteration. Maybe some part of their
| Zen4 APU's maybe in 3nm.
| mdasen wrote:
| AMD has said that 3nm will come with Zen 5c. The Zen 5 is set
| to launch in 2024 with the Zen 5c happening after that so most
| likely in 2025.
|
| Zen 4 just launched at 5nm after Apple had been using 5nm for 2
| years. It looks like Apple will be the only 3nm customer in
| 2023. Apple is not only selling a lot of phones, but they also
| need a follow-up to the M1/M2 processors (and the M2 is a very
| marginal improvement). I don't want to sound like I'm knocking
| the M1 because it's truly amazing to have an M1 laptop, but
| Apple is shipping a 2-year-old processor in all its laptops.
| While the Mac might not use as many chips as their phone biz,
| the chips are larger which means using up more of TSMC's
| capacity.
|
| Again, it took AMD 2 years to get to 5nm after Apple launched
| their 5nm chips. AMD might get to 3nm faster than they got to
| 5nm, but I wouldn't count on it. Qualcomm is sticking with 4nm
| for their 2023 Snapdragons. Samsung's transistor density for
| their "3nm" 2GAE is basically equivalent to TSMC's 4nm (while
| TSMC's 3nm is nearly 50% higher).
|
| If the question is "should I wait for something that's just
| around the corner," I'd have to say no. AMD does have a Zen 4c
| on its roadmap at 4nm, but 4nm can be a bit misleading since
| we're talking about TSMC improving density by around 6% (and
| Samsung's 4nm trailing TSMC's 5nm). So I wouldn't wait for
| "4nm" either.
|
| There's always uncertainty around when new stuff will happen,
| but it'll likely be more than 2 years before AMD moves to 3nm.
| Remember: we aren't even at the point where anyone has launched
| a 3nm part that you can buy. Let's say that Apple introduces
| something in April for their Macs and then launches new iPhones
| in the fall at 3nm. That's going to be using up a lot of TSMC's
| capacity through 2023 and into 2024. Qualcomm will want their
| 2024 chips to be 3nm in Spring 2024. So maybe late 2024 or 2025
| some 3nm capacity starts being available for AMD and they can
| launch 3nm Zen 5c then.
|
| Officially, this is what we have from AMD:
|
| Zen 4 - 5nm (2022) _editorial note: this ended up being
| September 27, 2022_
|
| Zen 4 V-Cache 5nm (2023)
|
| Zen 4C - 4nm (2023)
|
| Zen 5 - 4nm (2024)
|
| Zen 5 V-Cache - 4nm (2024+)
|
| Zen 5C - 3nm - (2024+)
|
| Could we see Zen 5c in 2024? Maybe, but it seems like a
| stretch. TSMC's 3nm seems a tiny bit behind schedule and given
| that Zen 5c is targeting "2024+", it just doesn't seem likely.
|
| So, there won't be an update to 3nm for Zen 4 and even Zen 5
| won't launch at 3nm.
| shmerl wrote:
| Using the node too soon can be a bad idea too, becasue it's
| going to be overpriced and that will be passed to the end
| user. I think AMD's pace of using the node is reasonable.
| It's Apple who is trying to jump the gun and use it sooner
| than normal making it cost way more than it could otherwise.
|
| TSMC charges way more for the newest node and then prices go
| down over time.
| beebeepka wrote:
| Zen 5 is the most likely candidate. Early 2024?
| shmerl wrote:
| Late 2024 may be? They generally have 2 years between
| generations.
| CSMastermind wrote:
| I don't know much about chip fabrication but reading wikipedia I
| see this:
|
| > The term "3 nanometer" has no relation to any actual physical
| feature (such as gate length, metal pitch or gate pitch) of the
| transistors. ... a 3 nm node is expected to have a contacted gate
| pitch of 48 nanometers and a tightest metal pitch of 24
| nanometers... "3 nm" is used primarily as a marketing term by
| individual microchip manufacturers ... there is no industry-wide
| agreement among different manufacturers about what numbers would
| define a 3 nm node
|
| So can someone who is more familiar with it help me understand
| what progress we're making in terms of the physical aspect of the
| chips? Is transistor density still increasing? Are we using
| different materials? At a physical level what's different about
| this generation of chips?
| [deleted]
| mk_stjames wrote:
| Look at FinFET transistors; this is the style of MOSFET
| currently employed at the smallest scales that I know of; This
| is what started calling the feature size of the process node
| smaller and smaller past 24nm- at least for recent processes,
| the smallest parts of the "fin" were getting down in the 10-7nm
| range, and smaller.... but this isn't the size of the whole
| transistor, it needs multiple fins on either side to make the
| gate structure. So this was what happened when we end from
| talking about MOSFET feature size to the single-digit process
| node sizes that are essentially marketing terms now verses
| actual gate size.
|
| There are actual density increases do to the packing of these
| type of FinFETs vs. more traditional MOSFETS. Thus the
| efficiency gains that have been happening. Among other reasons.
|
| Or at least that is my understanding.
| picture wrote:
| Different process nodes are not directly comparable across
| companies. Transistor density is still increasing.
| https://en.wikipedia.org/wiki/Transistor_count
|
| Smaller marketing numbers generally do relate to improved
| performance, usually from minor optimizations across the board
| like needing to move less charge to switch a transistor, etc.
| Also certain numbers introduce things like FinFET or gate-all-
| around that further increase performance.
|
| We are now past the point where just simple size shrink will
| yield significant benefit, due to physical limits no less. Most
| of the heavy lifting in terms of performance improvement comes
| from microarchitecture advancements
| marcosdumay wrote:
| Not only is the density still improving, but new processes come
| with better characteristics for dealing with current leakage,
| smaller voltage requirements, and faster charge carrier
| propagation.
|
| In other words, the transistors are being redesigned so that
| they work better.
|
| Things are just not moving on the same rate they used to be,
| and costs are going up instead of down. But there is plenty of
| movement.
| kernal wrote:
| If 3nm is merely a marketing term that has no relation to the
| distance between transistors than aren't we approaching a state
| where we could theoretically go into the negatives?
| colejohnson66 wrote:
| TL;DR: It's exponential, so it'll never go negative. After 3
| comes 2. After 2 (at least for Intel) comes 1.8, or 18
| Angstroms. See Wikipedia[0] for a reference.
|
| Longer answer: (someone correct me where I'm wrong)
|
| Historically, the number _was_ a measure of the size of the
| transistor. 250 nm process nodes were producing _planar_
| transistors that were about 250 nm across. A node was then
| defined as the measure that brought a set increase in
| performance. In other words, going from 250 nm to 180 nm was
| the same improvement as going from 180 nm to 130 nm.
|
| About the 45/32 nm mark, we reached the limits of making
| planar transistors. The machines couldn't get enough
| resolution to make them reliably. So, FinFET and others were
| invented as a way to increase performance to what was needed
| for the next generations. Essentially, the product has the
| performance of what planar transistors at said size would
| give, but they're not actually that size.
|
| However, now that a few node generations have passed, even
| that's not true anymore. Now, it's just a marketing term, and
| you can't even compare performance between different
| manufacturers. TSMC's 5 nm has different performance than
| Samsung's and Intel's. All you can know is that TSMC's 3 nm
| will be better than their 5 nm.
|
| [0]: https://en.wikipedia.org/wiki/List_of_semiconductor_scal
| e_ex...
| GeekyBear wrote:
| Indeed. You just drop down to smaller units.
|
| The Intel 8088 chip was made on a 3 micrometer process node
| and a decade later they had to measure in nanometers for
| the 486 which launched on an 800 nm process node.
| conjecTech wrote:
| Transistors at that scale are 3D rather than 2D, so the
| expected scaling ratios no longer apply. If you wanted double
| the density of a 2D transistor with 5nm features, you'd need to
| scale down to 3.5nm, but if you wanted to double the volumetric
| density in 3D, you'd only need to go down to 4nm.
|
| How do you make meaningful compare to past generations with
| that being the case? You could then just describe it in 2D
| terms, and refer to your 4nm process as 3nm. Then all of the
| same rules of thumb still hold.
|
| I assume this is responsible for at least some portion of the
| deviation and confusion, though maybe not all of it. Happy to
| be corrected if I'm wrong.
| jasonwatkinspdx wrote:
| The industry roadmap has adopted a new nomenclature to try to
| clear this up, but it remains to be seen if the major
| companies will adopt it.
|
| In any case, people who jump to saying these process node
| names are bullshit because they don't simply map to something
| like a wire width are kinda naively missing the point.
| Everyone in the industry understands what's going on and
| these fab node names emerged naturally as a shorthand way of
| describing changes to design rules that are a lot more
| complex and varied. That's still true today.
| 8note wrote:
| Media however, is not the industry, and the media has done
| a poor job of reporting based on industry names, rather
| than general public friendly names
| thechao wrote:
| Also, in practice, no one cares how "tall" the chip is --
| 100nm vs 200nm is ... unimportant. The result is that the
| _volume_ of the poly hasn 't changed much in the last ~10
| years. Transistors are still biggish; just with tiny
| footprints. (And really, it's pitch density: we can pack the
| poly tighter.)
| monocasa wrote:
| Not quite. We basically don't care about 3D density at the
| moment. The plane of the wafer is ultimately what matters
| from a density perspective. Right now we're actively cutting
| into 3D density heavily for small 2D density gains.
| conjecTech wrote:
| I assume you care about 2D vs 3D for different variables,
| no? I agree 3D, at least while H<<W, doesn't matter for
| clock speeds, but wouldn't it still play a significant role
| in the power characteristics, particularly things like gate
| capacitance? Genuinely curious. Going off of my memory of
| my Physics of CompE class ~10 years ago at this point.
| monocasa wrote:
| If the gates of the transistor are taking up all that
| space, but FinFETs and newer gate all around FETs have
| significantly sized voids in 3D space, you just can't
| practically use those voids for anything else without
| cutting into yields or having awful leakage issues.
| GeekyBear wrote:
| For the first version of TSMC 3nm, die sizes are projected to
| be ~42% smaller than TSMC 5nm and you have a choice of using
| ~30% less power or improving performance by ~15%.
|
| https://www.anandtech.com/show/17452/tsmc-readies-five-3nm-p...
| ajross wrote:
| Worth pointing out that (5/3)^2 is MUCH higher than the 1.42
| you cite though.
|
| It's definitely true that process scaling is employing tricks
| to increase density faster than feature size would predict.
|
| But it's even more true that node sizes from TSMC are now
| just totally made up nonsense. This is not remotely a full
| node kind of improvement.
| vardump wrote:
| I think almost no one cares.
|
| While it's unlikely scaling continues to this level, I got
| this funny idea: eventually the marketing gate size might
| become smaller than a single atom!
| monocasa wrote:
| We're close enough to see that on the horizon; about 2
| angstroms is the width of a silicon atom. Or well,
| distance between two nuclei in a silicon lattice. 'Width'
| of an atom is a tricky concept with many definitions.
| nsteel wrote:
| Unless your chip is mostly SRAM and lower power consumption
| isn't worth the massive cost of 3nm. It's not the normal easy
| decision for some designs.
| Latty wrote:
| Hence AMD using different process nodes for the stuff that
| scales and the stuff that doesn't at the same time with
| their chiplets, so they can get the best of both worlds.
| atq2119 wrote:
| Yes, transistor densities are increasing, interconnects are
| getting denser as well (that's what the "metal pitch" is
| about). There are also improvements in power consumption.
|
| I imagine there is more use of EUV and surely material
| compositions are getting tweaks as well.
|
| This is pretty much as it has been for the last couple of
| decades, though at a somewhat slower rate and with an
| increasing number of caveats. For example, the density of SRAM
| has recently been decreasing more slowly than the density of
| logic. What's particularly tricky are the economics: the cost
| per transistor isn't really going down much anymore.
| klelatti wrote:
| You might like 'The node is nonsense' on this topic and
| especially what sensible metrics might replace nm.
|
| https://read.nxtbook.com/ieee/spectrum/spectrum_na_august_20...
| bilsbie wrote:
| Wow so nothing in these chips is anywhere near atomic scale
| yet?
| [deleted]
| walnutclosefarm wrote:
| The mind boggles at what is being accomplished in semiconductor
| production at this scale. The smallest features in the (fin
| width, e.g.) in the 3nm process are roughly 5nm across. That's
| the diameter of a hemoglobin molecule. Or, to put it another way,
| it's about 40 silicon atoms. All this enables single chip
| processors with over 100 billion transistors, so, more
| transistors on laptop processor than neurons in your brain.
| Wholesale, that may run close to 1 ten millionth of a cent per
| transistor.
|
| All this, and yet the process for producing transistors in a
| planar layout on silicon (that is, an integrated circuit) was
| invented after I was born.
| bilsbie wrote:
| How are we doing in the chip shortage btw?
| Tempest1981 wrote:
| From the WSJ:
|
| > Chip Inventories Swell as Consumers Buy Fewer Gadgets -
| Semiconductor companies slash production plans amid weak demand
|
| > https://www.wsj.com/articles/chip-inventories-swell-as-
| consu...
|
| Although elsewhere, I read there's still a shortage of chips
| for cars:
|
| > Automotive chip shortages to continue throughout 2023,
| industry says
|
| > https://arstechnica.com/cars/2022/12/automotive-chip-
| shortag...
| xnx wrote:
| It's been a great run for the past few decades getting improved
| performance for "free" (i.e. through extremely advanced CPU
| engineering), and I'm glad they're still able to eek out another
| generation of hardware improvement. Curious how hitting
| limits/diminishing-returns in silicon will force innovation in
| architecture and software. Will be amazing to see the pendulum
| swing back toward software optimization. So much performance is
| being wasted or left on the table.
| kylehotchkiss wrote:
| there was a HN post yesterday about replacing Redux with
| ChatGPT, so I would have to agree maybe we can all aspire to
| write slightly leaner software with the massive performance
| laptops tend to have these days!
| NovaVeles wrote:
| This is something I think in the next 5 years will become a
| major thing. Broadly speaking from an OS level, the folks that
| optimize their software the best will see big benefits. I have
| advocated (lightly so) to some Linux folks that we should start
| moving to where the situation will be by the end of the decade.
| Optimize now before we have too.
|
| The pessimist (AKA Stallman) in me is thinking that vendors
| like Apple and Microsoft are going to use things like their
| Security processors to force people to buy new hardware.
| Software optimizations can potentially keep older hardware
| going for a lot longer, but by having an arbitrary security
| chip requirement - folks can be forced to purchase new hardware
| every few years as older model support is dropped. We are
| already seeing this in Windows 11.
|
| While we will not have a year of the Linux desktop, the ability
| for the speed optimizations to be more open to all people could
| be a sizable win for the platform. Provided the ability to do
| this isn't locked down.
| visarga wrote:
| Move compute closer to memory.
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