[HN Gopher] AMD's Zen 4, Part 2: Memory Subsystem and Conclusion
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       AMD's Zen 4, Part 2: Memory Subsystem and Conclusion
        
       Author : zdw
       Score  : 89 points
       Date   : 2022-11-08 13:34 UTC (9 hours ago)
        
 (HTM) web link (chipsandcheese.com)
 (TXT) w3m dump (chipsandcheese.com)
        
       | vardump wrote:
       | Nice. Plenty of insight in this article to better optimize for
       | Zen 4.
        
       | spamizbad wrote:
       | Very interesting. I wonder if we'll see a "Zen4+" that
       | ameliorates certain bandwidth constraints outlined in the article
       | (Better DRAM efficiency, increased L1D bandwidth).
        
         | Tuna-Fish wrote:
         | L1 bandwidth is very intimately tied to the core (it's really
         | more proper to talk about the bandwidth of the memory pipes
         | instead of L1), so that's not changing on a small revision.
        
         | paulmd wrote:
         | the bandwidth constraints will be significantly ameliorated by
         | v-cache skus, I'd imagine. I think AVX-512 tasks especially may
         | be among those that see benefits from v-cache: vector workloads
         | tend to imply larger working sets, and usually like cache and
         | bandwidth and lower latency as well.
         | 
         | (technically, the way AMD did v-cache in zen3 meant that cache
         | bandwidth didn't change, just higher hitrate, but, it doesn't
         | mean it will always be done that way in the future. RDNA3 saw a
         | shift from a focus on capacity/hitrate towards higher bandwidth
         | - infinity cache stayed the same size but much higher
         | bandwidth, which of course requires more transistors. Maybe we
         | will see something similar on Zen4 - you could have a Crystal
         | Well-style L4 or 6775R-style side-cache. Or even both a side-
         | cache and a big L3 on the same design - just stack them.)
        
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