[HN Gopher] TSMC approaching 1 nm with 2D materials breakthrough
___________________________________________________________________
TSMC approaching 1 nm with 2D materials breakthrough
Author : retskrad
Score : 254 points
Date : 2022-11-05 14:35 UTC (8 hours ago)
(HTM) web link (www.edn.com)
(TXT) w3m dump (www.edn.com)
| kken wrote:
| so this is again one of these "material x was slightly better in
| a lab experiment" -> "we conclude that it certainly can be used
| as part of a complex technology" press releases.
|
| I am not too fond of this, but obviously thats the easiest way to
| explain the significance of research results.
|
| Getting a new material into a semiconductor manufacturing process
| takes years or even decades. Whatever material will be in TSMCs
| "1nm" process, it is already known.
| [deleted]
| 323 wrote:
| I remember 15 years ago reading about EUV litography and a lot
| of people were saying that it looks like a pipe dream because
| they don't know of any way to produce a EUV light source strong
| enough, outside nuclear explosions and the like.
| kken wrote:
| It took 25 years to commercialize EUV. And that is from the
| point where a decision was made to industrialize it, not from
| the first scientific report about EUV radiation.
|
| edit, see Zeiss page on EUV:
| https://www.zeiss.com/semiconductor-manufacturing-
| technology...
| nomel wrote:
| It looks like small piece of tin is where the magic begins
| [1]:
|
| > An EUV system uses a high-energy laser that fires on a
| microscopic droplet of molten tin and turns it into plasma,
| emitting EUV light, which then is focused into a beam.
|
| is the spectrum naturally pure, or is there some
| filtering/selection going on?
|
| > The tricky thing with EUV light is that it's absorbed by
| everything, even air. That's why an EUV system has a large
| high-vacuum chamber in which the light can travel far enough
| to land on the wafer. The light is guided by a series of
| ultra-reflective mirrors
|
| The system uses 1MW of power!
|
| 1. https://medium.com/@ASMLcompany/a-backgrounder-on-extreme-
| ul...
| throwawaymaths wrote:
| There's filtering, but the spectrum should have (near)
| discrete wavelengths that it emits at selectively
| pas wrote:
| ahahah, that's not even the craziest thing about EUV. it's
| that the whole process has two actual laser shots, there is
| a preshot that heats the tin, forms a plasma that is shaped
| like a lens. and then comes the stronger, main shot.
|
| https://www.degruyter.com/document/doi/10.1515/aot-2017-002
| 9... see pre-pulse part.
| coldtea wrote:
| Yes, but do you remember all the BS PR releases about new
| "promising" techniques and materials that would
| "revolutionize" this or that process, that we read 15 and 20
| and 30 years ago, that never materialized at all?
| sylware wrote:
| nanoimprint (heard it is making a comeback in Japan), x-ray
| litography, mass electron beam litography...
| exyi wrote:
| So it took about 10 years to get into production. OP isn't
| claiming it's impossible, just that it's far from being
| practical. You could definitely say that about EUV 15y ago
| sillysaurusx wrote:
| (RIP memristors. Those have similarly been on the cusp of
| revolutionizing everything for ... I think over a decade now?)
| ewams wrote:
| Yup, I wrote about them from an HP conference in 2010 and
| remember being told about them for a roadmap item well before
| that: http://ewams.net/?date=2010/09/05&view=hptechforum2010
|
| Another one of those "right around the corner" things that is
| always coming soon.
| hinkley wrote:
| World is full of technologies that would be cool if you
| also had a Time Machine. But other tech outpaces is so if
| it is born behind it never takes off.
|
| Some of it is pretty fun for playing what if with
| (enforced) pastoralism. Using primitive materials with a
| modern understanding of them, instead of limiting yourself
| to historically accurate processes.
| agumonkey wrote:
| I take the slightly more patient approach with this. LCD
| used very old discoveries, something need to mature through
| a few industrial cycles before it gets discarded I guess.
| monocasa wrote:
| The rumor I heard was that HP licensed all the rights to the
| tech away and development has stalled since no entity can put
| their hands on enough of the IP to do anything with. : / So
| development has pretty much stalled since the last time HP
| showed of The Machine with memristors.
| bilsbie wrote:
| The patents should be nearly expired by now.
| monocasa wrote:
| A quick patent search shows that we still have a
| nontrivial amount of time on them.
| pencilguin wrote:
| Patents on fractal compression and related techniques are
| all expired now. There might still be people who remember
| how to use them. Do we see any use of it, now?
| mlindner wrote:
| IMO compression was a lot more important when we had
| modems and disk sizes measured in megabytes or single
| digit gigabytes. Once you have "good enough" compression
| then you solve most issues and in many areas where there
| used to be compression they've been increasingly removing
| it. Compression causes latency after all and some of the
| biggest impediments to processing speed now is latency.
|
| So unlike before, compression has stopped being a primary
| driving factor in the engineering of many types of
| devices and types of software.
| pencilguin wrote:
| Raw data compression was once an attractive application,
| but the method is more general. That said, streaming
| services still pay a great deal for bandwidth and storage
| in edge nodes. Cell- and keyframe-oriented video
| compression are reaching their limit.
|
| We are still interested in feature extraction and scene
| composition, which both benefit from more compact
| representation.
|
| To compete with hardware-assisted decoding in display
| hardware, fractal rendering would probably need to be
| coded to run in Vulkan.
| chc4 wrote:
| 3D XPoint, used in Optane memory, used memristors.
| ofrzeta wrote:
| It's funny that it's debatable what's a memristor and
| what's not: "Intel has stated that 3D XPoint does not use a
| phase-change or memristor technology, although this is
| disputed by independent reviewers." (Wikipedia)
| coldtea wrote:
| The renewed interest in them and the PR hoopla is closer to
| 14 years...
| jackmott wrote:
| hinkley wrote:
| Reading the article I wondered if tapered interconnects were
| the solution. Fat interconnects with thin fins? Probably harder
| to calculate inductance and capacitance, but these people deal
| with complexity all day.
|
| Not entirely sure how you'd avoid voids with tapers facing
| upward, but you can orient them in five out of six directions.
| And I've seen a few examples of the weird games they have to
| play with light to get the crisp corners they are after so
| maybe tapers would be easier?
| kken wrote:
| The actual discovery is reported in one of the last
| paragraphs:
|
| >The breakthrough relates to a new set of materials that can
| create monolayer--or two-dimensional (2D)--transistors in a
| chip to scale the overall density by a factor matching the
| number of layers. The teams at TSMC and MIT have demonstrated
| low resistance ohmic contacts with a variety of existing
| semiconductor materials, including molybdenum disulfide
| (MoS2), tungsten disulfide (WS2), and tungsten diselenide
| (WSe2).
|
| So it is a better way to make a contact to a semiconductor
| material that noone knows how to manufacture reliably on a
| large area wafer.
| arriu wrote:
| > Using non-silicon materials facilitates very tiny transistors--
| as small as 1 nm. However, as TSMC researchers acknowledge, the
| 1-nm process node is not likely to be used for years to come.
|
| Is anyone else using non-silicon materials yet?
| kragen wrote:
| The first transistors were made of germanium, and before
| germanium diodes were made from selenium and from an oxide of
| copper. Crystal radios commonly used Schottky diodes made of
| galena. Gallium arsenide is big business.
| ksec wrote:
| >Is anyone else using non-silicon materials yet?
|
| Gallium
| Maursault wrote:
| Gallium could only produce microchips larger than silicon.
| What we need are diamond microchips which should outperform
| silicon chips by a factor of 23K and be a third smaller.
| metadat wrote:
| Intriguing, do you have any good references or recommended
| reading about this?
| Maursault wrote:
| https://www.google.com/search?q=diamond+based+microchips
| metadat wrote:
| It seems we're still a long ways off from diamond
| semiconductors becoming mainstream. I wonder what the
| forcing function will end up being to dethrone silicon.
| Maursault wrote:
| Moore's Law seems like a decent candidate.
| hinkley wrote:
| Germanium is bigger, right? It's used in DSP chips and now in
| power transformers. The fact that it's used for high
| frequency circuitry has always made me wonder why we don't do
| large scale chips in it. Surely cheaper than the acrobatics
| we are doing for <5nm, no?
|
| It's used in current-dense applications and leakage current
| is out boogeyman with silicon.
| twosdai wrote:
| I have some background in this space in undergrad. Non Si
| materials are used in industry, germanium is used in some
| special applications and i believe its the #2
| semiconducting material, however it is harder to use than
| Si because it's very difficult to keep it clean of
| impurities. Not the doping kind.
|
| Source: I helped with a research project using Ge. Here's
| the paper if anyone is curious
| https://ieeexplore.ieee.org/abstract/document/8653561
| kken wrote:
| SiGe is used since the 90nm node as source/Drain material.
| e2e8 wrote:
| Several kinds of semiconductor materials are used for high
| power or high frequency applications but only at much larger
| process nodes. For example Gallium Nitride, InP, SiGe.
| transfire wrote:
| This is great and all, but in the end it just buys us a few more
| years. Something more radical has to come along eventually if we
| want to continue a Moore-esque pattern.
|
| I wonder what happened to plans for optical interconnects?
| ilaksh wrote:
| I think that is going to help but memristors will be a much
| bigger leap.
| lwneal wrote:
| At this rate they'll be manufacturing 0nm chips soon, and in a
| decade they'll be on -1nm.
|
| But despite the weird naming scheme, it's clear from transistor
| density [1] and GPU prices [2] that foundries are still making
| progress in transistors per dollar. That progress is just barely
| beginning to make large neural networks (Stable Diffusion, vision
| and speech systems, language model AIs) deployable in consumer
| applications.
|
| It might not matter whether your cell phone renders this page in
| 1ms or 10ms, but the difference between talking to a 20B
| parameter language model and a 200B net is night and day [3]. If
| TSMC/Samsung/Intel can squeeze out just one or two more nodes,
| then by the middle of the century we might have limited general-
| purpose AI in every home and office.
|
| [1] https://en.wikipedia.org/wiki/Transistor_count#GPUs
|
| [2] https://pcpartpicker.com/trends/price/video-card/
|
| [3] https://textsynth.com/playground.html
| alexose wrote:
| As a traditional "web dev" kind of hacker, I feel like I'm just
| sitting idly by while a massive transition happens underneath
| me.
|
| I understand roughly _why_ this shift is happening (machine
| language proving to solve a whole raft of hard problems) and
| _how_ it 's happening (specialized chip designs for matrix
| math). But I don't understand where it's all going, or how I
| can plug into it.
|
| It feels like a fundamentally different landscape than what I'm
| used to. There's more alchemy, perhaps. Or maybe it's that the
| truly important models are trained using tools and data that
| are out of reach for individuals.
|
| Does anyone else feel this way? Better yet, has anyone felt
| this way and overcome it by getting up to speed in the ML
| world?
| didibus wrote:
| The ML space is a lot easier to get into than before.
| Training and using models is more and more just like using
| any other library or framework. The hard algorithmic parts,
| the math, that's all being solved by academia and researcher.
|
| That said, getting hold of the data and the computational
| resources for training are barriers.
| largbae wrote:
| Just like every other technological advance, there is a sort
| of "food chain" that builds on top of these foundational
| technologies. You didn't have to work in cryptography to play
| a role in the massive proliferation of online commerce and
| banking. There were and are many, many conventional tasks and
| non-PhD-making innovations between cryptography existing and
| the wonderful low-friction commerce we now enjoy.
|
| Don't know how language translation models work? No problem,
| use one that someone else made to make a web framework that
| self-internationalizes to the user's browser default language
| without the site creator even knowing that language exists!
| alexose wrote:
| That's certainly true! I can use my current skillset to
| help connect users with new tech. And there have been many
| minor revolutions during the course of my career, many of
| which have been incorporated into the sort of work I do.
|
| I guess the difference (for me, anyway) is that this change
| isn't incremental. It's a fundamentally new type of
| computing-- One that comes with a totally new way of
| approaching problems. Listening to Andrej Karpathy talk
| about Software 2.0, for instance, it seems probable that ML
| has a place in many parts of the stack.
|
| It's possible I'm just projecting my insecurities, here,
| but my experience has been that changes to computing
| hardware usually result in changes across the entire
| industry. And this feels like a pretty meaningful change.
| ativzzz wrote:
| As a web developer, you are primed to create the interfaces
| to these ML tools (or any tool really). The browser is the
| most widespread UI application that nearly every single
| consumer computer has access to. You can work on literally
| anything that someone accesses via the internet, and the more
| AI/ML is made useful, the more people will need access to
| these products, the more web devs will be needed to build
| apps to use these products
| [deleted]
| Ptchd wrote:
| They aren't even really 1nm.... but either way, they could
| switch to pico-meter.....
| simpsond wrote:
| Intel chose Angstroms for their roadmap nodes: 20A = 2nm.
| algo_trader wrote:
| > clear from .. that foundries are still making progress in
| transistors per dollar.
|
| Are they?
|
| Home GPU price have been elevated due to crypto.
|
| Latest node CPUs are mostly opaque long-term contracts.
|
| The xxBN transistors chips are priced at $xx,000.
|
| If you have a (better) reference I would love to see it.
| superkuh wrote:
| Riiiight. 1 nm naming and ~15-20 nm pitch? Like the current 5nm
| stuff with a ~20-30 nm pitch and element size. ref:
| https://en.wikichip.org/wiki/5_nm_lithography_process
| gcanyon wrote:
| Wait -- based on the graphic at that page, should we be taking
| away that TSMC's and Samsung's shipping 6nm chips have only a
| very slight transistors/mm^2 advantage over Intel's 10nm chips?
| And just as importantly, that "XXnm" is nothing more than a
| marketing tool?!
|
| Hyperbole aside, it's undeniable that TSMC's chips for Apple
| have a greater computing-power/watt than Intel's chips -- but
| is that all they bring to the table? I don't mean to disparage
| power efficiency, it's awesome. But the question stands.
| ksec wrote:
| That graphics was made before Intel switched their naming.
| What you see Intel 10nm is now called Intel 7.
| [deleted]
| ur-whale wrote:
| Meaningless nm-based names is by now a well established fact of
| life in the semi industry.
|
| First order things that really matter are: - power dissipation
| - switching speed
|
| These rarely get mentioned in marketing materials.
| WithinReason wrote:
| This comment is there under every article that has _nm_ in it.
| For the millionth time, 1 nm should be read as "1 nm
| equivalent". The purpose of the naming is to continue to scale
| with density.
| audunw wrote:
| Getting so tired of this knee jerk complaint. Do you design
| standard cell libraries or analog ASIC IPs? If not, why would
| you care that "1nm" doesn't correspond to an actual dimension
| in the process? I work with ASIC design in a node where the
| name still matches the minimum gate length, and the number of
| times this has actual mattered to me is exactly zero.
|
| What _does_ matter to most people is transistor density and
| other performance metrics that actually have an impact on the
| product. The "Xnm" has always given a rough indication of the
| improvements in transistor density, and all the foundries has
| done is continue to name the nodes as if that's what matters...
| which is indeed the case.
|
| TSMC does sometimes call the nodes eg "N7" now. But nobody that
| matter cares because everyone understands that "7nm" is a
| marketing term.
| orangepurple wrote:
| It's a deception. So many people believe that it is the
| actual gate size, even educated folk not directly involved in
| semiconductor manufacturing.
| neogodless wrote:
| But even if you believe that, what do you do with that
| (mis) information?
|
| TSMC has continued to improve the process, and we've seen
| Apple and AMD design performant and efficient chips as the
| process improves.
|
| What changes if you don't understand the exact measurements
| involved?
| derefr wrote:
| A mass misbelief in the continuation of Moore's law into
| impossible sub-molecular scales. There is no more low-
| hanging fruit of "just make the optics more precise to
| make the lithograph smaller"; every process-node step
| we're taking now is rather a "side-step" involving
| solving increasingly-complex puzzles to make the same-
| sized features do more per molecule. It's code golf, at a
| hardware level. And as in code golf, there's a pretty low
| ceiling as to how intricately interwoven features can
| become. You can't eliminate the fundamental need to have
| all those features _in_ the code (circuit) in some sense.
|
| The actual visible effect of this is an economic one:
| we've gone from spending linearly more marginal CapEx per
| fab process-node upgrade, to spending _geometrically_
| more marginal CapEx. Each process node under 8nm has been
| twice as costly to design as the one before it. This is
| untenable.
| patmorgan23 wrote:
| I wonder if at some point the industry will shift to
| focus on higher yields, economies of scale, and software
| that uses the hardware more effectively.
| sjburt wrote:
| The particular measurements of the elements are not
| interesting, but the transistor densities are meaningful.
| I would expect a 1nm chip to achieve densities 100x a
| 10nm chip. That seems unlikely.
| spamizbad wrote:
| Who is it deceiving? It sounds like the only people who get
| "tricked" are laypersons; professionals do not.
| gpm wrote:
| Since when is it acceptable to trick laypeople,
| especially when laypeople are buying products with the
| false advertising (cpus...)?
| dymk wrote:
| 2x4 lumber.
| moooo99 wrote:
| > Since when is it acceptable to trick laypeople,
| especially when laypeople are buying products with the
| false advertising (cpus...)?
|
| This is such a HN issue. It's not tricking people because
| the vast majority of layman don't even care about node
| size, gate size or the manufacturing process. The number
| of times I have encountered a person outside of a tech
| bubble that cared about the manufacturing process of a
| CPU is exactly zero.
|
| What people do care about: does it work, is it fast, is
| it efficient and can I afford it. At least for
| performance and efficiency the marketing term does give a
| somewhat reliable indication of the generational gains.
| projektfu wrote:
| Investors. Even more sophisticated investors can be
| bamboozled by various claims. Because investors are
| usually trying to pick the future winners, they need
| these things as proxies to determine who is actually
| going to have the faster chips, or the lower costs, etc.
|
| Analysts are often not from the exact line of business.
| They may have a bachelor's in engineering, or something,
| but they're usually not domain experts beyond having
| studied the field from a business perspective and gotten
| used to its lingo. So, these things can be kind of
| manipulative. That said, it's par for the course. It's
| better than outright lying and bribing the analysts like
| in the 2000-2002 telecom bust.
| bee_rider wrote:
| If somebody has a bachelor's in EE and thinks the nm
| marketing value is an actual measurement they should see
| about getting a refund.
| orangepurple wrote:
| Investors talk about AI as if it is a real thing. Before
| that it was big data.
| bee_rider wrote:
| Colloquially lots of successful technologies have been
| referred to as "AI" and so it doesn't seem that
| unreasonable that investors could look into that kind of
| stuff. On the other hand, if somebody's investing
| strategy assumes, like, artificial general intelligence
| is coming soon -- investing involves risk and investing
| while stupid involves disproportionate risk I guess.
| joshcryer wrote:
| It's not a deception, the transistor itself is 1nm, the
| gate is larger because of physics. We're talking transistor
| and gates composed of 100~ freaking atoms with transistors
| being in the dozen or so. And we are complaining that
| they're using the "wrong metrics." We are nearing Moores
| limit, might as well rejoice when they bleed out another nm
| or so and can pack in a few billion more transistors.
| adrian_b wrote:
| The active part of a FET is the area that is under the
| gate or surrounded by the gate.
|
| It makes no sense to speak about a transistor that would
| be smaller than the gate, there is no such thing.
|
| Besides the active part, whose conductance is controlled
| and variable, the transistor includes parts that are
| either electrical conductors, like the source , the drain
| and the gate electrode, or electrical insulators.
|
| While those parts may be less important than the active
| part, they also have a major influence on the transistor
| characteristics, by introducing various resistances and
| capacitances in the equivalent schematic.
|
| What matters is always the complete transistor. The only
| dimensions in a current transistor that are around 1 nm
| are vertical dimensions, in the direction perpendicular
| on the semiconductor, e.g. the thickness of the gate
| insulator.
|
| The 2D semiconductors that are proposed for the TSMC "1
| nm" process are substances that have a structure made of
| 2D sheets of atoms, like graphite, but which are
| semiconductors, unlike graphite, which is a 2D electrical
| conductor.
|
| In this case the thickness of the semiconductor can be
| reduced to single layer of atoms, which is not possible
| with semiconductors that are 3D crystals, like silicon,
| because when they no longer form a complete crystal their
| electrical properties change a lot and they can become
| conductors or insulators, instead of remaining
| semiconductors.
|
| There is little doubt that for reducing the transistor
| dimensions more than it is possible with a 3D
| semiconductor like silicon, at some point a transition to
| 2D semiconductors will be necessary. It remains to be
| seen when that will be possible at an acceptable cost and
| whether such smaller transistors can improve the overall
| performance of a device, because making smaller
| transistors makes sense only when that allows a smaller
| price, smaller volume or higher performance of a complete
| product.
| wbl wrote:
| Isn't the gate part of the transistor? Or can I pack
| multiple FETs with a common gate in denser?
| Symmetry wrote:
| Language drifts. You might as well be upset that a British
| pound is longer a pound of silver. Or that people now use
| "very", "really", and "literally" as intensifiers rather
| than as claims to absolute truth.
| ksec wrote:
| > So many people believe that it is the actual gate size
|
| They never state it was the actual gate size in the first
| place. May be you should blame the media for it?
|
| And just to reply to parents.
|
| > TSMC does sometimes call the nodes eg "N7" now.
|
| It is not sometimes. TSMC has always been very careful and
| calling it N7 or N10 all the way back to 28nm era. What the
| media, marketing and other PR decided to call it are
| entirely different matter. This is especially problematic
| since ~2015 when they have gotten thousands if not millions
| times more media coverage.
| runeks wrote:
| It fooled The Economist. In this article TSMC is depicted
| in a chart as having >90% market share for "<10nm gate
| size": https://www.economist.com/asia/2022/05/26/taiwan-is-
| worried-...
| ur-whale wrote:
| So in summary, it's a damned lie, but since all the insiders
| participating in the cabal know it, it doesn't matter?
|
| Nice.
|
| And very consumer-friendly too, congrats.
| 323 wrote:
| Why doesn't the industry want to create a new metric?
|
| Like 2 bil transistors/square cm, let's call it 2 btsc or
| something. Surely they use something like that internally,
| why not publicly? Maybe there are different kinds of
| "transistors", some (CPU) bigger than others (RAM)?
| mjrpes wrote:
| Intel kind of tried this. In their presentations when they
| were struggling with 10nm, they tried focusing on
| transistor density count. That failed; people remained
| confused, especially with the (nm)+++ convention for same-
| node improvements. Intel gave up their old naming
| convention last year and are now using a marketing naming
| scheme similar to TSMC/Samsung.
|
| Moreover, density is only one metric of improvement, the
| other major one is power efficiency. Foundries want to
| market these improvements too.
| Symmetry wrote:
| The number of transistors per square centimeter will vary a
| lot depending on application. High speed logic is less
| dense than power efficient logic is less than RAM, for
| example. I suppose you could use a metric like a minimum
| size 8T SRAM cell but then you'd have complaints about
| foundries gaming the system by making process choices to
| shrink that at the expense of other structures.
| [deleted]
| zerohp wrote:
| I work in chip design on single digit "nm" processes.
|
| Interally we might say 5nm to refer generally and N5 or N5P
| to refer to a specific process. When you need more specific
| numbers you look it up. Exact design parameters are
| carefully protected trade secrets.
|
| Commenters on Hacker News care a lot more about this
| distinction than the engineers working with it. Nobody
| cares that it is not gate length or half pitch.
| 2OEH8eoCRo0 wrote:
| Exactly. I've read that they might not reflect actual size
| but still roughly reflect the density and efficiency you'd
| expect with that size.
| willmadden wrote:
| Watts consumed per MIPS is pretty hard to fudge for the
| layperson.
| bee_rider wrote:
| Depends on the instruction mix I guess, right? I'm sure you
| could come up with different benchmarks (think of the silly
| case, brancy hard-to-predict code on one of those super-
| long-pipeline Pentiums).
|
| Processors are just fundamentally complicated and boiling
| them down to a couple number is hard. Any modern one is
| pretty good and saying anything more than that -- depends
| on your workload I guess.
| ur-whale wrote:
| > Watts consumed per MIPS is pretty hard to fudge for the
| layperson.
|
| Hear hear.
| Symmetry wrote:
| That's only loosely a function of process node. Even for
| the same chip it will vary drastically depending on
| temperature, voltage, etc.
| [deleted]
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