[HN Gopher] Intel's Meteor Lake Chiplets, Compared to AMD's
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       Intel's Meteor Lake Chiplets, Compared to AMD's
        
       Author : rbanffy
       Score  : 83 points
       Date   : 2022-09-12 14:43 UTC (8 hours ago)
        
 (HTM) web link (chipsandcheese.com)
 (TXT) w3m dump (chipsandcheese.com)
        
       | Asmod4n wrote:
       | My brain is so used to the term chipset it refused to read the
       | headline correctly at first.
        
         | speed_spread wrote:
         | Buy some gum and wait till northbridges start using chiplets
         | too, you'll comparing chipset's chiplets chewing chiclets.
        
       | metadat wrote:
       | I wasn't familiar with the difference between a chiplet compared
       | to a typical microprocessor.
       | 
       | In case you also find this information helpful:
       | 
       | > A chiplet is an integrated circuit block that has been
       | specifically designed to work with other similar chiplets to form
       | larger more complex chips. In such chips, a system is subdivided
       | into functional circuit blocks, called "chiplets", that are often
       | made of reusable IP blocks.
       | 
       | https://en.wikichip.org/wiki/chiplet
       | 
       | https://en.m.wikipedia.org/wiki/Chiplet
        
         | toast0 wrote:
         | You can also think of this like a return to the earlier designs
         | with the CPU separated from the northbridge; there's a chiplet
         | for cpu cores, and another that serves the northbridge function
         | (memory, pci-e, etc), looks like intel has one for iGPU, and a
         | fourth that does I can't tell what (more I/O, I think?)
         | 
         | Smaller dies increase yield, and multiple dies allow you to use
         | different processes for different dies. The I/O may not benefit
         | as much from the cost of the smallest process and the smallest
         | process is often production limited, so doing that part of the
         | design in older processes saves money and increases production;
         | it makes the whole thing larger, but pin count is dictating
         | package size at the moment.
        
           | ajross wrote:
           | Or to "slot CPUs" of the P3 era, where the CPU and cache
           | management were shipped on the same PCB. Or to still earlier
           | designs where multiple VLIW chips were designed in tandem to
           | act as a single component. The original IBM RS/6000's had
           | (IIRC) a six-chip "CPU". There are comparatively few new
           | ideas in semiconductor packaging.
        
             | rbanffy wrote:
             | Now you made me remember Unisys' Micro-A. It was an
             | A-series mainframe on an ISA board. The CPU had 8 chips in
             | a single MCM (multi-chip module, as they called it) IIRC.
        
           | CamperBob2 wrote:
           | Everything old is new again: https://www.eevblog.com/2020/10/
           | 06/eevblog-1341-amazing-2500...
        
         | bee_rider wrote:
         | It is an interesting technology. It is basically a packaging
         | innovation, sounds pretty boring I guess, but larger chips have
         | a super-linearly bad effect on yield, so breaking up the design
         | into chiplets is very nice.
         | 
         | I wonder if anyone knows of a good place to look up Intel vs
         | TSMC yield numbers or defect density?
        
         | ant6n wrote:
         | I thought chiplet is about not doing a large monolithic chip,
         | but making a couple of small ones and connecting them together.
         | Smaller chips improve yield.
        
           | eklitzke wrote:
           | That is part of it, but it's not the full story. In earlier
           | multi-core CPUs each core was basically its own chip with its
           | own resources that could operate nearly fully independently
           | from the other cores (although not _completely_ independently
           | as you still need some cache coherency mechanism and usually
           | there would be at least a shared last-level cache). In the
           | chiplet model the chiplets are less independent and use more
           | shared resources, e.g. the chiplets might be designed so the
           | memory controllers are separate from the chiplets themselves
           | and shared between multiple chiplets.
           | 
           | There's obviously kind of a gray area and what makes
           | something a chip or a chiplet isn't necessarily precisely
           | defined, but the name "chiplet" implies a model with smaller
           | cores that use more shared resources.
        
         | rbanffy wrote:
         | You can also think of it as a bunch of very small components
         | (CPU, IO, HBM) on a very small PCB that's more or less another
         | larger chip, but with larger features as well (so that it
         | doesn't pay the yield penalties of a large area on a bleeding
         | edge process).
        
       | [deleted]
        
       | myself248 wrote:
       | Is it just me, or is the SoC tile way larger than anyone
       | expected? From TFA:
       | 
       | > A SoC tile contains most of the functionality found in the
       | system agent in current Intel client CPUs.
       | 
       | Given that this tile utterly dwarfs the CPU cores themselves,
       | what all is going on in there? Why is it so enormous? How much of
       | it do we understand?
        
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       (page generated 2022-09-12 23:01 UTC)