[HN Gopher] TinyTapeout: Get your design on an actual ASIC
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TinyTapeout: Get your design on an actual ASIC
Author : bajsejohannes
Score : 98 points
Date : 2022-08-27 10:40 UTC (12 hours ago)
(HTM) web link (mailchi.mp)
(TXT) w3m dump (mailchi.mp)
| PointyFluff wrote:
| bajsejohannes wrote:
| For anyone who wants to dip their toe in integrated circuits
| (ASIC), this project provides a way to get a tiny (~200 gate)
| project onto a physical chip. You can do the whole thing in the
| browser. Deadline for submission is September 1st.
| alain94040 wrote:
| What can one do with 200 gates? I struggle to think of anything
| interesting.
| amelius wrote:
| Hashing?
| mysterydip wrote:
| It mentions a possible set of dip switches and a 7 segment
| LED. You could make a puzzle game of "lights out" where only
| a certain combo of switches would have all the segments off.
| r3013 wrote:
| I suppose it depends on one's interests.
|
| For example one could try to clone many of these: https://en.
| wikipedia.org/wiki/List_of_7400-series_integrated...
|
| Another fun project idea. Make a 1bit processor slice. Then
| show how many slices can make a larger system. Similar to:
|
| "Using LSI processor bit-slices to build a PDP-11--A case
| study in microcomputer design"
| https://dl.acm.org/doi/pdf/10.1145/1499402.1499444
| alain94040 wrote:
| Maybe an idea: Could I use this to put a secret key in the
| gates, with some mechanism to prevent brute-force breaking?
| So my own personal Yubikey essentially.
|
| Not sure how to protect against replay, with only 200
| gates...
| cmrdporcupine wrote:
| A full 6502 is only like 900 gates. One could do a neat
| project with separate ALUs chips, control logic, etc, like
| AM2900-style.
|
| From Googling, it sounds like the 74181 ALU chip was only ~75
| gates or so https://en.wikipedia.org/wiki/74181. And the
| AM2901 something like ~500
| ahmadmijot wrote:
| Are you the author? I've read the slides but can't find the
| details. What kind cell library this project use? I know from
| someone in the IC design industry said that it's kind of hard
| to access all the tools and semiconductor IPs without some kind
| of NDA or agreement with library vendors and foundry.
| bajsejohannes wrote:
| I'm not the author, and honestly know very little about
| ASICs. But apparently enough to get a design onto this
| tapeout! :D
|
| If q3k's answer wasn't sufficient, maybe you can find more
| answers in the github repo that builds everything?
| https://github.com/mattvenn/wokwi-verilog-gds-test
|
| Otherwise, there's a discord where the author (Matt) very
| active: https://discord.gg/rPK2nSjxy8
| q3k wrote:
| (Not the author, but in the know.)
|
| This uses the Skywater 130 process. It's backed by an open
| source PDK (SKY130B), and is going to be taped out via an
| Efabless shuttle, just like OpenMPW shuttles sponsored by
| Google.
|
| The difference between this and a 'plain' OpenMPW shuttle is
| that this can fit a ton of tiny/toy/demo designs, enabling a
| lot of people to get their toes wet with ASIC design without
| having to take up a 'large' shuttle spot.
|
| https://skywater-pdk.readthedocs.io/en/main/
| thrtythreeforty wrote:
| The Skywater shuttles are never full, to the best of my
| knowledge. However, it is a lot of work to get off the
| ground with the PDK (synthesis and physical design for
| chips is a totally separate set of skills on top of logic
| design), so if this further lowers the barrier to entry
| then that's fantastic
| rrss wrote:
| The last 3 or 4 openmpw shuttles have been full.
| thrtythreeforty wrote:
| That's great to hear, I'm glad to be corrected.
| [deleted]
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