[HN Gopher] Details on AMD's Quirky Chipset Solutions for AM5
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Details on AMD's Quirky Chipset Solutions for AM5
Author : walterbell
Score : 55 points
Date : 2022-05-22 20:59 UTC (2 hours ago)
(HTM) web link (angstronomics.substack.com)
(TXT) w3m dump (angstronomics.substack.com)
| formerly_proven wrote:
| Interesting to note that, just from memory, this means most of
| the increased I/O possibilities actually come from the CPU
| itself, not the chipset. 2x7 W also means that chipset power
| remains pretty much the same compared to X570, though two chips
| will lend themselves better to effective passive cooling.
| glowingly wrote:
| Sounds like a decent approach. On the current AM4 setup, the
| chipset had an x8 link allocated (at least in dmi), but only x4
| was ever hooked up. Based on information here, too bad they
| weren't able to build on that and avoid the daisy chain setup
| altogether (x4 direct to each "southbridge").
| AaronFriel wrote:
| What an unusual departure from their previous generation. The
| prosumer and just-below HEDT market loved the Ryzen chips for
| their generous amount of PCIe lanes. The x670 looks to -
| confusingly - reduce CPU-available lanes/slots and risk
| contention on the chipset for peripherals and storage. No one
| will want to debug a daisy chained M.2 or USB 4.0 connection
| suddenly slowing down.
|
| If true and it's also true that the non-Pro Threadripper line is
| gone, this leaves a large gap for Intel to exploit with Alder
| Lake X. The Threadripper line's 60+ lanes of PCIe effectively
| took over the HEDT market. Intel not only couldn't compete on
| performance, but for storage arrays, ML workstations, other
| important niches, they were the only viable option.
|
| I'm hoping the rumors of Threadripper's demise are wrong, and
| both Intel & AMD are able to compete in the space. That's best
| for consumers, not this alternating pendulum. (See: Threadripper
| price hikes.)
| __alexs wrote:
| PCI-E 5.0 has a ridiculous amount of bandwidth for consumer
| purposes. They just don't need as many lanes.
| zamadatix wrote:
| Threadripper/HEDT is a different line, socket, and chipset.
| This is for the consumer stuff and looks to have the same
| number of CPU direct lanes as last generation, just higher
| speed.
| AaronFriel wrote:
| I am aware and I believe I accurately described first these
| rumored changes to the Ryzen line, and second the rumored
| cutting of the consumer Threadripper line.
|
| Is there some way I could edit my comment to make it clearer?
|
| > This is for the consumer stuff and looks to have the same
| number of CPU direct lanes as last generation, just higher
| speed.
|
| I think I disagree, as the PCIe4.0x4 slot off the chipset is
| now an additional step removed (& subject to greater
| contention). But I digress, my point is that AMD risks
| leaving a gap in their market coverage by doing two things:
|
| 1. There are rumors they are no longer competing in consumer-
| accessible high lane count CPUs/chipsets.
|
| 2. They have an opportunity with the next gen Ryzen to close
| the gap by (1.) offering more lanes at 4.0 speed (they could
| offer 40 CPU-attached lanes!) but by moving to 5.0
| exclusively, they limit expansion options.
|
| If both leaks/rumors are true, it suggests a missed
| opportunity.
| zamadatix wrote:
| I think it'd be a little clearer to avoid referring to any
| of the Threadripper family as "below HEDT" or the sort.
| That's the Ryzen 9 family, even the lowest end plain
| Threadripper was always HEDT. Nothing here has changed for
| the consumer market.
|
| I won't comment much on the rumour side but overall I'm not
| as worried about whether things are named "Threadripper" vs
| "Threadripper PRO" as this never set the price floor
| anyways E.g. a 16 core Ryzen Threadripper PRO 3950X was
| $350 MSRP higher than a 16 core Ryzen 9 3950X.
|
| Whether or not they ever release anymore low price high
| lane count options is an interesting question but that AM5
| was supposed answer this and because it didn't AM5 is a
| departure from the past is just too many layers of
| assumption, rumour, and leaks to make any useful discussion
| about.
| toast0 wrote:
| I don't see the departure?
|
| AM4 cpus have an x16 for GPU, an x4 for NVMe storage, and an x4
| for chipset, according to the article, AM5 cpus will have an
| x16 for GPU, an x4 for NVMe storage, and adds an x4 for for
| USB4 or more NVMe storage, and then an x4 for chipset, plus
| whatever the USB stuff means.
|
| The rumored chipset takes that x4 and offers two x4s, four
| sata/3.0 x1 ports, and 6 usb3, six usb 2 ports.
|
| There were a bunch of different chipsets for am4, most of which
| didn't have more connectivity than that. If you build the x670
| link two of the new chipsets, and consider the added x4 from
| the cpu, you still have pretty similar connectivity as the
| x570, but you only have 12 lanes squeezing into the x4 for
| chipset instead of 16. There's certainly a discussion to be had
| about the CPU lanes being 5.0 and the chipset lanes (including
| uplink to the CPU, apparently) being 4.0; but while there's not
| much in the way of PCIe 5.0 devices, it's mostly hypothetical.
| If PCIe multiplexers weren't immensely expensive, the 24 CPU
| lanes at PCIe 5.0 would be equal to 48 lanes of PCIe 4.0 (plus
| 4 more for the chipset), and pretty close to the Zen2
| Threadrippers's 56 + 8. Lack of cheap multiplexers means that's
| not really how the cookie crumbles though.
| cududa wrote:
| Here's where this gets cool. If you've ever got into pro level
| "over clicking" RAM channels to maximize performance, this would
| leave you scratching your head.
|
| Won't the timing of each chipset on each board need to be
| painstakingly individually configured to avoid latency from a
| "default" profile used in all chips (which inherently vary
| between every batch)? Yes, yes they would.
|
| Unless you had an automated solution. And if you have an
| automated way you could optimize CPU and DDR timing instead of
| using "buffered"/ "safe" latency settings to accommodate any
| manufacturing variance.
|
| Well turns out AMD has a method for that. And given the necessity
| for a tech like this to make daisy chained chipsets work, it
| would seem this isn't an idle patent. AM5 systems are basically
| going to get a 10-20% performance bump due to that optimization.
| Which is wild.
|
| https://www.tomshardware.com/news/amd-patents-automatic-memo...
| wmf wrote:
| _Won't the timing of each chipset on each board need to be
| painstakingly individually configured to avoid latency from a
| "default" profile used in all chips (which inherently vary
| between every batch)?_
|
| No, because PCIe works completely differently from RAM. PCIe is
| a packet-based protocol that's very latency-tolerant. (Multi-
| lane PCIe links may require deskew but that's a standard
| feature that has existed all along.) I think it was Marcan who
| tunneled PCIe over RS-232 and the chips didn't even notice.
| cududa wrote:
| Well the chipset also handles shuttling RAM channels..
| zamadatix wrote:
| x16+x4 has worked fine for consumers at PCIe 4.0 since GPUs
| aren't benefiting from the bandwidth so it should work fine with
| PCIe 5.0 and even if you bifurcate for x8 x8 + x4 so you can have
| another high speed addon card of some sort that's still ~250 Gbps
| of bandwidth per card which is more than any home or gaming setup
| will be bottlenecked by (workstation and server sure but those
| will be different boards).
|
| I'm not quite sure the dual linked chipset option for the high
| end really gets anyone anything. I mean sure, double all your
| ports... where half now have 2x the latency penalty to the CPU
| and all in all they are sharing less bandwidth than your primary
| storage slot has alone.
| wtallis wrote:
| > where half now have 2x the latency penalty to the CPU
|
| Are _any_ of the typical uses for those IO lanes latency-
| sensitive enough for that to matter at all? Consumer-grade
| networking, SATA storage, and most USB use cases all involve
| latency high enough that one more PCIe switch wouldn 't be
| noticed.
| Strom wrote:
| How much extra latency are we talking here? Anyone have any
| actual numbers?
| jleahy wrote:
| I would guesstimate low single digit microseconds (and
| guesstimating latency is pretty much my job).
|
| Typical USB poll rates are 10-100 _milliseconds_. AMD made
| a perfectly sensible choice.
| justsomehnguy wrote:
| I would say what in a typical consumer setting even 2x
| latency for the NVMe drives wouldn't be noticeable,
| especially considering there is one directly on the CPU.
| zamadatix wrote:
| The NVMe off that second slot in particular is what's going
| to be painful for that market segment. If it weren't the
| topology that was only used specifically for the high
| performance market segment I'd say it doesn't matter but I'd
| be willing to bet most in that segment would actually want
| that 2nd x4 lane direct to the 1st chipset like last gen, not
| to the a second chipset just so they can have even more built
| in USB and SATA ports.
|
| But who knows, maybe "I have a great gaming PC, it's got 25
| USB ports!" (yes, that's the actual number) is more
| marketable than actually tuning for performance.
| potiuper wrote:
| Amazing no vendor has come out with a X300/Knoll mini ITX board
| with a PCI x16 along with NVME slot.
| rasz wrote:
| >their 600-series chipset
|
| No, the chipset is in the Ryzen CPU. What they mean is a
| Southbridge used by board manufacturers for market segmentation
| purposes.
|
| >AMD's Ryzen line of client Desktop processors don't even need a
| 'chipset'
|
| Amazing, an article stating the truth for once!
|
| >Despite this, nearly all Desktop motherboards still contain a
| chipset, but in its modern iteration serve as I/O expansion hubs
|
| and back to muddying the water. No, "chipsets" are used for
| market segmentation, and AMD is complicit with gems like this:
|
| https://www.itworldcanada.com/article/amd-zen-3-processors-w...
|
| https://www.extremetech.com/computing/320548-amd-will-suppor...
|
| https://www.anandtech.com/show/14477/amd-confirms-pcie-4-not...
|
| https://www.eteknix.com/some-asus-x470-and-b450-motherboards...
|
| not to mention overclocking lockouts
|
| all this bullshit depending on what ASMedia IO dongle connects
| over PCIE bus on the motherboards.
|
| >dual-source these chipsets
|
| and proceeds to explains how there will be none of that with
| exclusive ASMedia once again :)
|
| >Low-end, Mid-range, High-end
|
| ah yes, back to artificial segmentation based on limited BW 4x
| PCIE switch while CPUs provide plenty of dedicated PCIE lanes.
|
| >"X670E" branded motherboards will require the primary PCIe and
| M.2 slots to support PCIe 5.0 linkrate. The chipset itself is
| identical to X670.
|
| and now we are at making up totally fake name for a non existent
| product X670E to upmarket PCIE 5.0, sweet!
|
| >designing only a single piece of silicon to span across multiple
| market segments, it is much more cost-effective to design for the
| mass market middle-end solution and double up for the high-end
| rather than designing a larger, more expensive die that fits the
| requirements of the top end
|
| spilling truth by accident once again. Yes, AMD is selling us the
| same cheap solution under different names for different prices,
| and we should be thrilled!
| cebert wrote:
| I was under the impression that AM5 would support PCIe 5.0
| instead of 4.0. I'm becoming less excited about this next
| generation from AMD than I was a few months ago.
| cududa wrote:
| What specific benefit are you expecting from PCIe 5
| rasz wrote:
| it will, but only if you pay extra for fake "X670E" chipset
| while getting same X670 motherboard, but with unlocked pcie
| 5.0.
| wmf wrote:
| It will support PCIe 5.0 on the slots directly connected to the
| CPU, but probably only on X670E motherboards. Note that there
| will be very few 5.0 devices on the market and you won't be
| able to notice the performance difference.
| shantara wrote:
| How much of this information was confirmed, and how much are
| rumors and speculations? With such a radical change from the
| previous generation, it seems more prudent to wait the remaining
| couple of days until Computex to be absolutely sure.
| wmf wrote:
| This is a rumor, but it's rare to see extremely specific yet
| wrong rumors.
| dangle1 wrote:
| There's some photos at Tom's:
|
| https://www.tomshardware.com/news/amd-x670-motherboard-diagr...
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