[HN Gopher] VeriGPU: GPU in Verilog loosely based on RISC-V ISA
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VeriGPU: GPU in Verilog loosely based on RISC-V ISA
Author : btdmaster
Score : 67 points
Date : 2022-04-23 17:10 UTC (5 hours ago)
(HTM) web link (github.com)
(TXT) w3m dump (github.com)
| lizardactivist wrote:
| Very cool, but can someone remind me what "GPU" means again?
| Frenchgeek wrote:
| Generic Processing Unit, it seems.
| [deleted]
| yjftsjthsd-h wrote:
| > Internal GPU Core ISA loosely compliant with RISC-V ISA. Where
| RISC-V conflicts with designing for a GPU setting, we break with
| RISC-V.
|
| Very amateur question: I thought RISC-V added vector extensions
| so you could use it directly for GPU/TPU chips without having to
| fragment the ecosystem?
| colejohnson66 wrote:
| The V extension is more akin to the various SIMD extensions of
| x86 (SSE/AVX) or ARM (NEON) than a GPU system. I'm sure one
| could make a GPU based on RV-V, but the extension is more GPGPU
| like than a pixel/shader pipeline.
| Sirened wrote:
| Neat! Looks like it's very much in its early stages (no
| concurrent execution/threads yet) but it's so great to see FOSS
| digital design work in an industry dominated by huge players
| gnufx wrote:
| Perhaps also see the (OpenPOWER-based) Libre-SOC effort
| https://libre-soc.org/
| tux3 wrote:
| Worth noting this is targeting ML applications, so I don't think
| you'll be able to display even a text console with it for the
| foreseeable future.
|
| But I love that this is even in the realm of possibilities!
| There's no reason we couldn't, in principle, have a small open-
| source GPU taping out on the free Skywater shuttle, and I am here
| for it!
| milkey_mouse wrote:
| It's funny that we've gotten to the point that a "graphics-less
| GPU" is actually useful. Perhaps they should call it something
| else...
| zmgsabst wrote:
| Like a "tensor processing unit" or TPU?
|
| A RISC-V open source TPU would be a big innovation in AI and
| scientific computing.
| petrohi wrote:
| We work on an open source tensor processing unit at
| https://tensil.ai. It is not RISC-V based since only a
| handful of very simple instructions is needed for
| expressing data flows typical in ML.
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