[HN Gopher] Apple's M1 Ultra comes with a design limitation that...
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       Apple's M1 Ultra comes with a design limitation that was overlooked
       by Apple
        
       Author : retskrad
       Score  : 18 points
       Date   : 2022-04-13 21:24 UTC (1 hours ago)
        
 (HTM) web link (twitter.com)
 (TXT) w3m dump (twitter.com)
        
       | musicale wrote:
       | Good thing that we have Twitter since Apple doesn't know what
       | they're doing, right? ;-)
       | 
       | And it's too bad that apparently the page size can't be changed
       | for larger memory systems to reduce TLB misses (at the expense of
       | fragmentation) which is one traditional solution that doesn't
       | require software changes. 16KB seems like a very small page size
       | on a 64GB system. If we scaled an 8MB VAX with 512B pages up to
       | 64GB it would have a page size of something like 4MB.
        
       | notreallyserio wrote:
       | So the "design limitation" in the chip can be overcome by
       | updating apps to support Apple's TBDR tile memory system that was
       | presumably created to maximize processor performance? Am I
       | understanding the design limitation correctly?
        
       | sounds wrote:
       | https://threadreaderapp.com/thread/1514295682777059329.html
       | 
       | The tweets refer to Tile-Based Deferred Rendering (TBDR) [1] as
       | compared to Tile-Based Immediate Rendering (TBIR).
       | 
       | Here's another take on it:
       | https://docs.imgtec.com/Architecture_Guides/PowerVR_Architec...
       | 
       | Note that TBIR appears to be a term the author just made up to
       | refer to apps that have not be specifically optimized for the
       | Apple M1 Ultra GPU architecture.
       | 
       | [1]
       | https://developer.apple.com/documentation/metal/resource_fun...
        
       | Damogran6 wrote:
       | Any time there's a massive change in architecture, it should be
       | expected improvements will be found in tweaking.
        
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       (page generated 2022-04-13 23:02 UTC)