[HN Gopher] What's harder to find than microchips? the equipment...
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What's harder to find than microchips? the equipment that makes
them
Author : wallflower
Score : 96 points
Date : 2021-11-06 14:01 UTC (8 hours ago)
(HTM) web link (www.wsj.com)
(TXT) w3m dump (www.wsj.com)
| bserge wrote:
| It's amazing how wasteful the whole industry is.
|
| Now you have soldered CPUs in laptops - a great way to ensure
| they get replaced often ($$$ for Intel/etc) and end up in a dump
| in Africa somewhere, where no one will see or use the vast
| majority of it, ever again.
|
| What a waste.
| cgb223 wrote:
| Has any startup attempted to solve this problem by creating new
| chip making hardware?
|
| I know it takes years to even get one out the door but crazier
| moonshots have been funded and the ROI potential to break up a
| relative monopoly must be huge
| hugh-avherald wrote:
| It's hard to think of any enterprise that would be less
| suitable for a startup.
| theli0nheart wrote:
| If a startup can build nuclear fission reactors or supersonic
| jets, it's likely that a startup could do this too.
| [deleted]
| ajsnigrutin wrote:
| Chip making is not a relatively-well documented software
| project with a bunch of people with knowledge available to get
| in the labour market
|
| Chip making is a bunch of very very very specialized equipment,
| a lot of real black magic, and a few people who actually know
| what they're doing.
|
| This makes it worth more to find existing, experienced
| manufacturers and try to get them to make more, than to
| reinvent a very complex wheel, with so much research involved,
| that the chip crises may be over, before the first devices
| reach production
| 0898 wrote:
| Dumb question: how do chip makers predict their roadmap? If they
| know they'll be able to do still finer etching in 4 years, what's
| stopping them from doing it now? How can you not be able to do
| something today, but still know fairly accurately you'll be able
| to do it in future?
| ISL wrote:
| Through product-management and estimation.
|
| At scale, R&D can, to a limited extent, be commoditized.
| Companies/organizations (think particle-accelerators, etc.)
| have substantial experience bringing new technologies into
| production. If a new process has been proven in the lab and
| estimates exist for the speed with which each technology-
| demonstration milestone can be reached, one can credibly
| estimate when a new technology can reach the market. It is an
| inexact science, but all science is inexact.
|
| With sufficiently accurate estimates and conservative
| allowances for uncertainty and schedule-slippage, one can
| reliably do this. Intel did so for _decades_ , using Moore's
| Law as a roadmap.
| petra wrote:
| To create a chip requires machines from many vendors and
| integrating them. So there's a collaborative roadmap for the
| industry.
|
| A single vendor couldn't speed this process by much, because he
| won't have those missing tools.
| j_walter wrote:
| Many 20+ year old fabs are still expanding and the old machines
| are very hard to come by. We have recently even started
| converting 300mm machines to run 200mm wafers because those
| machines are easier to find. Not every chip runs on the latest
| and greatest technology. For instance there is no need for a 5nm
| power management chip...180nm is perfectly capable of handling it
| efficiently.
| cnasc wrote:
| > For instance there is no need for a 5nm power management chip
|
| But like what if you did it anyway? I remember pondering this
| while looking at some guitar pedal schematics. A lot of them
| use ICs that are basically ancient. Do newer processes have
| anything to offer (even if it wouldn't be cost-efficient)?
| lmilcin wrote:
| For these kinds of chips there is usually nothing the new
| process can offer other than higher development costs, higher
| production costs, longer cycle times, lower yields, higher
| noise levels and higher EMC susceptibility.
|
| A chip that fits its package comfortably at 180nm will not
| benefit from converting it 5nm process at all.
|
| The main reasons to get with a smaller process node is to put
| more transistor on the same area, use less power or reduce
| the size of the chip, that's it. A power management chip does
| not qualify.
|
| There is one more reason: if you are already invested in
| smaller process node or when it is difficult to find
| machinery for older process.
| bserge wrote:
| Cost efficiency is the key, though. It'd be kind of like
| newer 2.5" SSDs, the actual drive takes up a fraction of the
| space inside. Just without the benefit of being cheaper.
|
| Power savings would pale in comparison to cost and for many
| components like amps, bigger = more power.
| dehrmann wrote:
| I'm sure the answer is "it depends," but when do parts get so
| small that you stop getting higher part yield per wafer because
| the component just gets too small?
|
| Are there reliability or ruggedness concerns where some use
| cases prefer older processes?
| [deleted]
| xxpor wrote:
| I assume this is a non starter since no one (that I know of) is
| doing it, but is there a reason you can't "just" apply a 200mm
| mask on top of a 300mm wafer? If the limitation is the 300mm
| wafer costs more and makes the chips too expensive, how much
| would the cost have to increase in order to make it worth it?
| ((300mm^2 _pi) - (200mm^2_ pi))/(300mm^2*pi) % roughly?
| haneefmubarak wrote:
| The kind of precision and accuracy tolerances you need in
| these machines basically make it so that everything has to be
| exactly right. The 200mm mask won't have a place to "fit
| correctly" in the 300mm machine and so you won't be able to
| get the precision and accuracy you need. Remember: a silicon
| chip is actually made of many layers, which means many masks
| (1 mask per layer). Additionally, the method by which 200mm
| masks and 300mm masks are actually used in the etching
| process can vary significantly because of physics that I
| honestly don't have a phenomenal insight into.
|
| Making larger wafers drives prices up, because the process of
| making a monocrystal larger and larger, but I don't think
| that's a major cost factor except for super cheap chips. The
| minimum cost of a 200mm wafer is about $2/in^2 and the
| minimum cost for a 300mm wafer is about $3/in^2, in case
| that's helpful.
| mjevans wrote:
| The pad size for external wires might dominate the design
| for extremely simple designs, however couldn't a
| combination of these factors help?
|
| * Shrink the average node size 1-2 times (E.G. 180nm to 90
| or 45nm)
|
| * Combine popular combinations of products into a single
| package that can have interlinks cut by laser or skipped at
| the metal traces stage?
|
| * Generally consolidate similar products within fewer
| variations?
|
| The slightly greater cost of the physical wafer is supposed
| to be offset by the increased machine throughput and the
| die shrinks possible, as well as ideally fewer defects by
| using newer processes. An extremely inexpensive set of
| processes for 300mm wafers would also be a good target for
| long term bulk semiconductor production.
| makomk wrote:
| I assume there's other equipment still in use on the line
| that can only handle 200mm wafers, otherwise it'd make sense
| to upgrade to 300mm and take the extra capacity increase -
| the masks are stepped across the wafers anyway, there's no
| reason in principle they can't just add more chips to fill in
| the extra area if they have the ability to process 300mm
| wafers.
| brennanpeterson wrote:
| Masks are not whole wafer , except in some packaging cases.
| The mask illuminates a 25*35 area, for both 300mm and 200mm.
|
| Masks are not a significant expense for most processes. Nor
| is the bare wafer. It is all the process steps that drive the
| cost.
|
| 300mm qafer
| nanomonkey wrote:
| The equipment also requires folks that know the in's and out's of
| engineering for the equipment. This can be as much of a bottle
| neck as finding the equipment itself.
|
| There are many Universities that are running old equipment for
| the EE departments.
| analog31 wrote:
| Why bother learning how to make hardware when you can make a
| better living writing software?
|
| </s>
| mfg4u wrote:
| I don't think the /s is necessary. Many EE's go through much
| of the same coursework as CS students. For young EE's why
| would they go into the HW world when they could make so much
| more money working in SW. I am an EE and I am considering
| making the jump to SW as my daily workflow is already about
| 60% SW work.
| xxpor wrote:
| And yet we're complaining about having to know git internals in
| order to use it :)
| dehrmann wrote:
| I wonder what I should buy in the microchip glut of 2023.
| ksec wrote:
| Yes, but The Equipment That Makes Them also requires chips to
| function as well :)
|
| AFAIK There are at least five members on HN working in those
| equipment company.
| ur-whale wrote:
| https://archive.md/rJ21X
| chuckSu wrote:
| Thank you :-)
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