[HN Gopher] Cache splash in Telum means seventh heaven for POWER11?
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Cache splash in Telum means seventh heaven for POWER11?
Author : classichasclass
Score : 30 points
Date : 2021-09-05 05:00 UTC (2 days ago)
(HTM) web link (www.talospace.com)
(TXT) w3m dump (www.talospace.com)
| buildbot wrote:
| I was really surprised by this cache design, in a good way. It's
| a very interesting innovation, one of those that is simple once
| you hear it but nobody (as far as I know?) has tried this
| approach yet. I think it's very clever for a large distributed
| system like the Z mainframes;
|
| It would be fun to build some Network on Chip FPGA designs using
| this approach to model how it would perform!
| api wrote:
| One thing I wish modern multi core chips had was some way to
| just directly transfer core to core. That would be really
| interesting, though I suppose it might be really hard to make
| it play nice with OS abstractions. Might only be useful in
| specialized HPC applications.
| tux3 wrote:
| Well.. you can play cacheline ping pong between cores today!
| No going to DRAM, straight from core to core.
|
| But I'm curious what sort of algorithm you have in mind that
| needs to spend a lot of time moving data between cores.
|
| Embarassingly parallel algorithms are the ideal. The less
| communication, the less Amdhal's tax costs you.
| jyounker wrote:
| Everything old is new again. In the 90's Kendall Square
| Research built modular supercomputers based around using
| nothing but cache.
|
| https://en.wikipedia.org/wiki/Kendall_Square_Research
| addaon wrote:
| Previous discussion about the cache structure (not in the context
| of POWER) here: https://news.ycombinator.com/item?id=28401737
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(page generated 2021-09-07 23:00 UTC)