[HN Gopher] Warp-V: A RISC-V CPU Core Generator Supporting MIPS ISA
       ___________________________________________________________________
        
       Warp-V: A RISC-V CPU Core Generator Supporting MIPS ISA
        
       Author : watchdogtimer
       Score  : 42 points
       Date   : 2021-07-19 12:12 UTC (10 hours ago)
        
 (HTM) web link (www.cnx-software.com)
 (TXT) w3m dump (www.cnx-software.com)
        
       | LoveLeadAcid wrote:
       | Hard to extract any useful information from that blog post. Was
       | it written by a bot?
       | 
       | EDIT: I am the article writer's father.
        
       | rahen wrote:
       | Interesting. Anyone knows what's the benefit of TL-Verilog
       | compared to a next gen HDL like nmigen?
       | 
       | Robert Baruch used it extensively for his own RISC-V CPU
       | implementation. Its channel is well worth watching for those
       | interested in CPU design.
       | 
       | https://www.youtube.com/c/RobertBaruch/videos
        
       ___________________________________________________________________
       (page generated 2021-07-19 23:01 UTC)