[HN Gopher] Electron tube New Automatic Computer
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Electron tube New Automatic Computer
Author : edent
Score : 60 points
Date : 2021-07-04 09:56 UTC (13 hours ago)
(HTM) web link (ena.computer)
(TXT) w3m dump (ena.computer)
| formerly_proven wrote:
| At first I thought just the tubes for this must have cost several
| thousand dollars, but it turns out you can buy these 6N3Ps for as
| little as 50 cents a pop (allegedly Soviet NOS), which probably
| makes these the lowest-cost vacuum tubes around, by far!
| jonnycomputer wrote:
| Still, $0.50 for a single logic gate is pretty expensive,
| considering how many you need to construct all the circuits
| you'd need. You'd need 6 for a single D flip-flop...
| dangerbird2 wrote:
| I see about 220 tubes in that pic, and I'd guess he'd need at
| least twice that to replace bad/broken tubes. I bet there are
| more that aren't visible, so it should cost a few hundred
| dollars. Still, it's a huge steal compared to what a
| comparable tube computer would have cost back in the 60s.
| analog31 wrote:
| I noticed that he used a tube that's widely available but not
| in demand for use in guitar amplifiers. Smart move.
| eMGm4D0zgUAVXc7 wrote:
| > The Ena.computer has 8 inputs, 8 outputs plus two handshakes.
|
| What is the meaning of "handshakes" in this context?
| Animats wrote:
| He has an interface for two Pong joysticks.
| tyingq wrote:
| "Handshakes" usually means "how a protocol handles direction of
| data". For typical serial communication, that means either
| hardware handshakes via RTS/CTS ( Request to Send and Clear to
| Send) lines, or software handshakes via XON/XOFF characters in
| the stream.
|
| Since he's using "handshakes" in the context of "8 inputs / 8
| outputs", I'm assuming it means he has 8 outputs that can be
| high or low, 8 inputs that can read high or low, plus 1 more
| input and one more output to handle something like CTS/RTS.
|
| Basically, he's saying 2 lines are dedicated for hardware flow
| control.
|
| And, the 8 inputs/8 outputs seem to be used like a IEE 488 (HP-
| IB) parallel port. He mentions talking to a Commodore PET
| through its parallel port. That's a little confusing because
| HP-IB requires 3 handshake lines, and he specifically says he
| has "a pair" of handshake lines. I guess it's just his own
| custom protocol.
| orbital-decay wrote:
| RAM is always the bane of machines like this. You can build a
| working CPU with a relatively few discrete elements, but a usable
| amount of RAM always needs many times more. Core memory is
| probably the only sane option in projects like this, save for
| Williams tubes.
| TedDoesntTalk wrote:
| > Most important of all is to have a lovely wife, who knows
| you're daft as a brush, and that life together is brilliant.
|
| He has his priorities straight.
| jonnycomputer wrote:
| >The Ena.Computer is designed using 550 double triode 6N3P
| electron-tubes, all configured as identical 5 input NOR gates.
| Registers and counters are built from these single NOR gates and
| combined into master/slave D type flip flops, an 8 bit ALU, and
| all latches and buffers.
|
| In my computer science program, we had an old school prof who
| insisted we build a virtual CPU using only fundamental
| components. No VHDL for us! We wanted a JK flip flop? Here are
| the logic gates. Wire them up baby. The only thing that came for
| free were the logic gates, a clock, and probes. Some students
| complained about it; and I get it, it was a very old-school way
| of doing things. But I can say that I intimately understood my
| 5-staged pipeline CPU, because I designed it from the ground up,
| and spent hours wiring every component. I also had plenty of time
| cursing myself for some stupid design decisions I made along the
| way. The only thing that might have made it better if we were
| tasked with actually building it out in actual hardware. I'm a
| fan of those homebrew cpu's out there. Maybe not practical from
| computing perspective any more, but sooo cool.
|
| http://homebrewcpu.com/
|
| https://hackaday.io/project/178826-pineapple-one
| wallacoloo wrote:
| The VLSI equivalent version of this is to build a cpu by
| manually placing the N/P diffusion regions, the gate poly, the
| metal contacts, and the metal wires in your EDA program. The
| conclusion is to either export it as a spice model and simulate
| it electrically, or actually get it fabbed on an old process
| node.
|
| Week 1-2: construct your own standard library of logic cells
| (I.e. design the layout of the not gates, nand gates, etc).
|
| Week 3-4: compose these std cells into latches and flip flops.
|
| Week 5-6: verilog implementation of your cpu. Used primarily as
| a model.
|
| Week 7-10: lay out your CPU. Everything from the register file
| to the ALU. Placed and routed by hand.
|
| Week 11: SAPR the instruction decoder/control logic and then
| integrate it into your custom layout. Ok so you can't brag
| about your layout being 100% custom anymore, but you learned
| more by doing it this way :P
|
| Week 12: write an assembler; compile a simple assembly program.
|
| Week 13-14: run it on the CPU; explore the limits of your CPU
| (clock speed, etc).
|
| Well the timeline will vary, but that's the idea. I think the
| only feasible way to do that is as a team project spanning
| multiple quarters. Honestly one of the most rewarding projects
| I've ever done & would recommend to any prof out there who
| wants to push their students.
| madengr wrote:
| We did the same in my EE program, though we were allowed to use
| a ROM for the microcode and some 8-bit registers from the TTL
| family. I never had time to build it either as it's too much
| for a single semester class.
| vlahmot wrote:
| I spent many hours in http://www.cburch.com/logisim/ during my
| program doing the same thing. It was a great feeling to finally
| get a sub component correct and then copy it around in the next
| layer up.
| jonnycomputer wrote:
| yeah, that looks similar to the software I used. yes, and
| great feeling too, because I was in control of my design
| (only spec was it had to have at least 5 stages in pipeline).
| I remember the first time I got a program running. Felt
| really good.
| tyingq wrote:
| >who insisted we build a virtual CPU using only fundamental
| components. No VHDL for us!
|
| A little convoluted, but apparently a couple of people have
| coaxed Verilog and/or VHDL into understanding 74xx logic chips:
| http://pepijndevos.nl/2019/07/18/vhdl-to-pcb.html
| gus_massa wrote:
| It looks like an interesting weird project, and I like weird
| projects. But I don't understand from the site:
|
| Is it working? Is there is video? Is at least some subsystem
| build in the real world?
| jonnycomputer wrote:
| Yea, I'd like to see a demo.
| Animats wrote:
| He seems to still be working on the memory part.
|
| That apparently will not be retro technology, like a delay
| line, but just modern RAM of some kind.
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