[HN Gopher] Taking students from schematic to silicon in one sem...
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Taking students from schematic to silicon in one semester (2018)
[pdf]
Author : teleforce
Score : 101 points
Date : 2021-06-19 13:38 UTC (9 hours ago)
(HTM) web link (people.eecs.berkeley.edu)
(TXT) w3m dump (people.eecs.berkeley.edu)
| pclmulqdq wrote:
| In college, I had the privilege of taking and then teaching a
| VLSI class like this. It was an amazing experience and I think
| more engineers need to go through the process. When I get the
| chance (no IP agreement with a company), I want to do the
| efabless thing that Google is offering
| weinzierl wrote:
| I studied Engineering Physics and specialized in semiconductor
| engineering. In our courses we made a working SAW-filter. We did
| everything from design, to silicon fabrication,to bonding,
| packaging and testing. It was a fun project, I learned a lot and
| I still have my little SAW-filter.
|
| To add a little background, I think there are two main reasons
| that made this project possible:
|
| 1. Our professor was very good at organizing donations of
| decommissioned equipment from the industry. The department was
| well funded and that certainly must have helped a lot, but what
| made all the difference is that our professor was _much_ better
| at getting in-kind donations than most of his colleagues.
|
| 2. Selecting the SAW-filter as a project was a brilliant idea. It
| enabled us to make a completely working product while teaching us
| basically most essential steps that are used in the production of
| real active semiconductor components too. At the same time it
| allowed us to skip the really hard, expensive or dangerous tasks
| like high-resolution masks, multiple masks and the whole business
| of doping.
| georgeburdell wrote:
| Stanford had (has?) a class where you actually fabricate the
| chips in their cleanroom. I've heard from people who took the
| class that you'd have to reserve individual pieces of fabrication
| equipment at all sorts of weird hours (not unlike a real chip
| plant) and work shifts to get done in time
| jarmitage wrote:
| There should be another version of nand2tetris called sand2nand
| quantumwannabe wrote:
| I'm surprised that this course was only offered first in 2017 and
| isn't a degree requirement. I'm not an electrical engineer, so I
| don't know if these skills are taught in a different and less
| hands-on manner, but it seems like being able to work in a team
| with tight deadlines and being able to design a chip for
| manufacturing are key skills that an engineer should have.
| opencl wrote:
| There's generally a required class that involves implementing a
| chip design on an FPGA.
|
| A very small fraction of people getting EE degrees actually go
| into IC design and it would probably be very expensive/a
| logistical nightmare to put such a large number of students
| through this type of class.
| reportingsjr wrote:
| IC design/VLSI classes where you do this are offered at most
| decent universities with an EE department. These classes are a
| big part of why MOSIS was founded, which has been around for
| about 40 years now.
|
| I'm thinking probably less than 25% of EEs take this track
| though, because there is a lot more to EE than just IC design.
| rcfox wrote:
| Yeah, I took a similar course around 2010. It was a fourth
| year course and had a ton of prerequisites, so you pretty
| much had to plan to take it from second year.
|
| Most EE students I knew decided to specialize in power
| generation since it was seen as the easiest path to a cushy
| job.
| ttul wrote:
| We had a course like this at my engineering school. Cutting your
| own chip is a fantastic journey. My partner made a key mistake
| along the way by reversing the layout of an op amp, but I was
| able to model his mistake and show the prof that I had figured it
| out on the lab bench. Full marks. It was fun.
| fxtentacle wrote:
| I would love to do such a project in my free time, but I can't
| afford the needed software tools.
| reportingsjr wrote:
| Google and efabless are offering free IC production for people
| who want to do open source chip design for what it's worth:
| https://www.efabless.com/open_shuttle_program
|
| This started last summer and a number of interesting designs
| have been produced, pretty much entirely with free, open source
| tools.
|
| Join the slack and ask around for projects that need help if
| you want to dip your toes in this sort of work!
| https://invite.skywater.tools/
| jjoonathan wrote:
| Is it still digital only?
|
| I'm interested, but almost entirely on the analog side -- I'd
| love to design a NLTL, VCO, or distributed amplifier. I have
| the utmost respect for the crowd looking to scale RISC-V
| cores, but it's just not my scene.
|
| EDIT: I took a look at
| https://github.com/yrrapt/caravel_amsat_txrx_ic_mpw2 and
| there are clearly some analog projects in there. Evidently I
| should have hustled harder!
| madengr wrote:
| No, they have a harness called Caravan that has no I/O
| buffers. I calculated Ft=65 GHz on this process and have a
| 1-15 GHz amp working in simulation (pre-extraction), though
| I don't know if I'll have time to apply for the next run.
| fxtentacle wrote:
| From reading the documentation, it appears that their open
| source tools start with Verilog RTL files that have been
| simulated with Synopsys VCS, Mentor Graphics Questa, or
| Cadence Incisive Enterprise Simulator.
|
| That said, one could probably use the free (but not open
| source) Vivado HL WebPACK to create and test the RTL design
| and then follow along with the Skywater tools. But that way,
| the way towards the FPGA would still be closed source and
| only the path from FPGA on to ASIC would be open.
|
| Further down the rabbit hole, I read about
| https://github.com/icebreaker-fpga/icebreaker which appears
| to be a tiny Teensy-compatible open source FPGA board with
| accompanying open source tools. Yay!
|
| Thank you very much for bringing all of this to my attention
| :)
| madengr wrote:
| I'm taking the Zero to ASIC course, and it's a fully open
| source flow from Verilog to GDS.
| [deleted]
| wrycoder wrote:
| _Hide buffer time in the schedule: we were able to manufacture a
| chip in large part because we never discussed the foundry's true
| due date with students. Instead we opted to build tolerance into
| the schedule and kept students aiming for an earlier deadline._
| SlowBall wrote:
| Having worked in the industry (thankfully not anymore),
| surprisingly that's how it works in the real world as well.
| Engineers are given a tape-out date that they have to meet, but
| managers have some hidden extra slack just in case.
| folkhack wrote:
| Anecdotally, the "II. Overcoming Student Misconceptions" section
| really rang true to how I've experienced working with highly
| academic engineers - ie: wanting to put blinders on only working
| on their component, late is assumed OK, not anticipating +
| coordinating with other teams interfaces/integration boundaries,
| not designing with real-world implementation in mind.
| carlosf wrote:
| "The tendency to spend valuable hours practicing perfectionism
| resulted in weeks of timeline delays and loss of design
| integration and verification time."
|
| Students in a nutshell.
| [deleted]
| kayson wrote:
| This would be a really great experience but only for a small
| subset of EEs who make it into RF/Analog IC design. And even so,
| I'd much rather see strong fundamentals than tape out experience
| in a new college grad because the latter is much easier to teach
| than the former. In fact, with no prior tape out experience (but
| an MSEE), I was responsible for a couple of tape outs after only
| a year of experience at my first IC design job.
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