[HN Gopher] Porting the Oberon system to the RISC-V [video]
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       Porting the Oberon system to the RISC-V [video]
        
       Author : pjmlp
       Score  : 45 points
       Date   : 2021-06-01 17:05 UTC (5 hours ago)
        
 (HTM) web link (www.youtube.com)
 (TXT) w3m dump (www.youtube.com)
        
       | 0xcde4c3db wrote:
       | NB: Some versions of the Oberon system were specified with a soft
       | CPU called RISC5, which has nothing to do with the RISC-V ISA.
        
         | johndoe0815 wrote:
         | To avoid exactly that confusion is what made Rikkes talk a bit
         | challenging... :)
        
       | johndoe0815 wrote:
       | This is the previous discussion about the project, Rikke
       | presented it at FossNorth today -
       | https://news.ycombinator.com/item?id=25497002
        
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       (page generated 2021-06-01 23:01 UTC)